Commit graph

24 commits

Author SHA1 Message Date
Blue Swirl 77b2bc2c09 x86: avoid AREG0 for exceptions
Add an explicit CPUX86State parameter instead of relying on AREG0.

Merge raise_exception_env() to raise_exception(), likewise with
raise_exception_err_env() and raise_exception_err().

Introduce cpu_svm_check_intercept_param() and cpu_vmexit()
as wrappers.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-06-28 20:28:08 +00:00
Aurelien Jarno 2355c16e74 target-i386: fix SSE rounding and flush to zero
SSE rounding and flush to zero control has never been implemented. However
given that softfloat-native was using a single state for FPU and SSE and
given that glibc is setting both FPU and SSE state in fesetround(), this
was working correctly up to the switch to softfloat.

Fix that by adding an update_sse_status() function similar to
update_fpu_status(), and callin git on write to mxcsr.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-01-11 09:55:28 +01:00
Andre Przywara 31501a714b target-i386: implement lzcnt emulation
lzcnt is a AMD Phenom/Barcelona added instruction returning the
number of leading zero bits in a word.
As this is similar to the "bsr" instruction, reuse the existing
code. There need to be some more changes, though, as lzcnt always
returns a valid value (in opposite to bsr, which has a special
case when the operand is 0).
lzcnt is guarded by the ABM CPUID bit (Fn8000_0001:ECX_5).

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-23 17:10:36 +02:00
Andre Przywara 1b050077d2 target-i386: add RDTSCP support
RDTSCP reads the time stamp counter and atomically also the content
of a 32-bit MSR, which can be freely set by the OS. This allows CPU
local data to be queried by userspace.
Linux uses this to allow a fast implementation of the getcpu()
syscall, which uses the vsyscall page to avoid a context switch.
AMD CPUs since K8RevF and Intel CPUs since Nehalem support this
instruction.
RDTSCP is guarded by the RDTSCP CPUID bit (Fn8000_0001:EDX[27]).

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-04 14:46:34 +02:00
Jan Kiszka a23978077b x86: Add support for resume flag
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2009-05-22 10:50:37 -05:00
pbrook a7812ae412 TCG variable type checking.
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-17 14:43:54 +00:00
balrog 2436b61a6b SYSENTER/SYSEXIT IA-32e implementation (Alexander Graf).
On Intel CPUs, sysenter and sysexit are valid in 64-bit mode. This patch
makes both 64-bit aware and enables them for Intel CPUs.
Add cpu save/load for 64-bit wide sysenter variables.

Signed-off-by: Alexander Graf <agraf@suse.de>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5318 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-25 18:16:18 +00:00
blueswir1 79383c9c08 Fix some warnings that would be generated by gcc -Wredundant-decls
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5115 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-30 09:51:20 +00:00
bellard 94451178b6 HLT, MWAIT and MONITOR insn fixes (initial patch by Alexander Graf)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4746 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-18 09:32:32 +00:00
bellard db620f46a8 reworked SVM interrupt handling logic - fixed vmrun EIP saved value - reworked cr8 handling - added CPUState.hflags2
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4662 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-04 17:02:19 +00:00
bellard 914178d34b 32 bit SVM fixes - INVLPG and INVLPGA updates
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4660 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-04 13:53:05 +00:00
bellard 872929aa59 SVM rework
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4605 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-28 16:16:54 +00:00
bellard 437a88a51c proper helper definition registering (all targets must do that)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4530 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-22 16:11:04 +00:00
bellard 1b9d9ebb8a cmpxchg8b fix - added cmpxchg16b
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4522 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-22 09:52:38 +00:00
bellard bd7a7b33df convert eflags manipulation insns to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4515 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-21 17:07:20 +00:00
bellard cec6843e87 converted LSL/LAR/VERW/VERR to TCG - force 16 bit memory access for LSL/LAR
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4513 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-21 16:25:27 +00:00
bellard 07be379fb1 converted INTO/CMPXCHG8B to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4510 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-21 13:29:45 +00:00
bellard 6191b05901 BSR/BSF TCG conversion
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4477 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-17 18:44:58 +00:00
bellard b6abf97df1 converted condition code supprot to TCG - converted shift ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4470 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-17 12:44:31 +00:00
bellard b8b6a50b55 converted more helpers to TCG - fixed some SVM issues
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4459 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-15 16:46:30 +00:00
bellard b5b38f61b8 converted more helpers to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4447 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-12 22:05:13 +00:00
bellard 19e6c4b8bc converted x87 FPU ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4444 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-12 19:10:44 +00:00
bellard 5af451868c converted SSE/MMX ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4441 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-12 16:47:36 +00:00
bellard 57fec1fee9 use the TCG code generator
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3944 c046a42c-6fe2-441c-8c8c-71466251a162
2008-02-01 10:50:11 +00:00