aurel32
9cd38c2372
target-alpha: fix double TCG variable allocation
...
Noticed by Chris Krumme.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5671 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-11 11:30:04 +00:00
aurel32
6223246ad9
target-alpha: fix the return value of stl_c/stq_c
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5649 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-08 09:10:39 +00:00
aurel32
57a92c8e36
target-alpha: fix locked loads/stores
...
Fix reading of cpu_lock in gen_qemu_stql_c, original patch from Laurent
Desnogues.
A new flag was added to gen_store_mem to allocate local temps instead
of temps; this flag should be set when the tcg_gen_qemu_store callback
uses brcond before using the temps or else liveness analysis will get
rid of the temps.
This also adds lock printing in cpu_dump_state which can help
debug.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5645 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-07 14:00:24 +00:00
aurel32
1304ca878a
target-alpha: Fix ret instruction
...
Hopefully pine doesn't corrupt this patch, I've had problems recently.
For an alpha "ret" instruction, of the type
ret $26
The return was being ignored. This is because in translate.c
register $26 (the return address) was being over-written with the current
PC before it could be jumped to. Thus the ret was ignored.
This patch just re-orders things so the return address is processed before
it is over-written with the current PC.
(Vince Weaver)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5638 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-06 09:16:57 +00:00
aurel32
1b581c440b
target-alpha: use the new TCG logical operations
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5502 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-21 11:29:11 +00:00
aurel32
8bb6e981e0
target-alpha: convert palcode ops to TCG
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5360 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-30 06:45:44 +00:00
aurel32
f4ed86794c
target-alpha: convert locked load/store to TCG
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5359 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-30 06:45:34 +00:00
aurel32
fe2b269a4f
target-alpha: misc fixes
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5355 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-29 17:21:37 +00:00
aurel32
f18cd2238d
target-alpha: convert FP ops to TCG
...
- Convert FP ops to TCG
- Fix S format
- Implement F and G formats (untested)
- Fix MF_FPCR an MT_FPCR
- Fix FTOIS, FTOIT, ITOFF, ITOFS, ITOFT
- Fix CPYSN, CPYSE
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5354 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-29 17:21:28 +00:00
aurel32
023d8ca21f
target-alpha: factorize load/store code
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5353 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-29 17:21:17 +00:00
aurel32
b03d0971b3
target-alpha: switch most load/store ops to TCG
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5255 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-18 15:31:27 +00:00
aurel32
04acd30726
target-alpha: convert remaining arith3 functions to TCG
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5254 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-18 13:45:14 +00:00
aurel32
a1cf28f469
target-alpha: fix one more literal sign issue
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5251 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-18 10:13:19 +00:00
aurel32
dfaa85834f
target-alpha: instruction decoding simplification
...
Use a litteral value of 0 when rb31 is used. This reduces the tests
in the instruction decoding. Also remove almost unused corner cases.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5250 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-18 10:11:26 +00:00
aurel32
01ff9cc8fe
target-alpha: convert cmp* instructions to TCG
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5249 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-18 09:24:25 +00:00
aurel32
adf3c8b6e9
alpha: fix a missing literal sign issue
...
Reported by Tristan Gingold
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5248 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-18 09:17:13 +00:00
aurel32
6ad025921c
target-alpha: switch a few helpers to TCG
...
Switch a few helpers to TCG and implement RC and RS instructions
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5247 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-18 00:02:17 +00:00
aurel32
b3249f630e
target-alpha: convert byte manipulation instructions to TCG
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5246 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-17 22:04:52 +00:00
aurel32
9c29504eb7
alpha: convert cmov and bcond to TCG
...
Patch mostly by Tristan Gingold
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5245 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-17 22:04:44 +00:00
aurel32
1ef4ef4e64
target-alpha: small optimizations
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5238 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-16 22:44:25 +00:00
aurel32
6ba8dcd773
target-alpha: fix TCG register names
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5237 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-16 22:44:17 +00:00
aurel32
30c7183b67
target-alpha: convert some arith3 instructions to TCG
...
Replace gen_arith3 generic macro and dyngen ops by instruction specific
optimized TCG code.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5236 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-16 22:44:10 +00:00
aurel32
ae8ecd4231
target-alpha: convert arith2 instructions to TCG
...
Replace gen_arith2 generic macro and dyngon ops by instruction specific
optimized TCG code.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5235 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-16 22:44:02 +00:00
aurel32
9e85e9bdcf
alpha: fix lit sign
...
according to the alpha arch reference, the literal field of an operate
instruction is unsigned:
If bit <12> of the instruction is 1, an 8-bit zero-extended literal
constant is formed by bits
<20:13> of the instruction. The l teral is interpreted as a positive
integer bet ween 0 and 255
and is zero-extended to 64 bits.
This patch fixes the mis-interpretation of the literal field.
(Tristan Gingold)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5211 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-14 16:09:15 +00:00
aurel32
29d26d20e5
fix alpha cmovxx instruction
...
The CMOV instruction is defined by the alpha manual as:
CMOVxx Ra.rq,Rb.rq,Rc.wq !Operate format
CMOVxx Ra.rq,#b.ib,Rc.wq !Operate format
Operation:
IF TEST(Rav, Condition_based_on_Opcode) THEN
Rc ← Rbv
The current qemu behavior inverses Ra and Rb. This is fixed by this
patch.
Signed-off-by: Tristan Gingold <gingold@adacore.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5171 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-05 19:07:53 +00:00
aurel32
4f821e1757
alpha: convert a few more instructions to TCG
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5152 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04 04:36:20 +00:00
aurel32
3761035f2c
alpha: directly access ir registers
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5151 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04 04:36:00 +00:00
aurel32
496cb5b921
convert of few alpha insn to TCG
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(based on a patch from Tristan Gingold)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5150 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04 04:35:40 +00:00
blueswir1
a5f1b965da
Fix warnings that would be generated by gcc -Wstrict-prototypes
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5021 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-17 20:21:51 +00:00
ths
2cfc5f17d3
Small cleanup of gen_intermediate_code(_internal), by Laurent Desnogues.
...
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4891 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-18 18:01:29 +00:00
pbrook
b2437bf267
Add missing static qualifiers.
...
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4801 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-29 12:29:56 +00:00
pbrook
2e70f6efa8
Add instruction counter.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4799 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-29 01:03:05 +00:00
aurel32
d2856f1ad4
Factorize code in translate.c
...
(Glauber Costa)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4274 c046a42c-6fe2-441c-8c8c-71466251a162
2008-04-28 00:32:32 +00:00
aurel32
ca10f86763
Remove osdep.c/qemu-img code duplication
...
(Kevin Wolf)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4191 c046a42c-6fe2-441c-8c8c-71466251a162
2008-04-11 21:35:42 +00:00
bellard
57fec1fee9
use the TCG code generator
...
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3944 c046a42c-6fe2-441c-8c8c-71466251a162
2008-02-01 10:50:11 +00:00
bellard
aaed909a49
added cpu_model parameter to cpu_init()
...
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3562 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-10 15:15:54 +00:00
j_mayer
f071b4d3ca
Alpha coding style and inlining fixes.
...
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3462 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-28 00:56:24 +00:00
j_mayer
bb6f6792bf
Allow Alpha target to use supervisor and executive mode micro-ops.
...
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3389 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-14 08:50:17 +00:00
ths
5fafdf24ef
find -type f | xargs sed -i 's/[\t ]$//g' # on most files
...
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3173 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-16 21:08:06 +00:00
ths
ce62e5ba09
Fix tb->size mishandling, by Daniel Jacobowitz.
...
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3160 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-11 10:04:58 +00:00
ths
08ab123c2d
Avoid compiler warning.
...
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2935 c046a42c-6fe2-441c-8c8c-71466251a162
2007-06-03 17:10:43 +00:00
j_mayer
e96efcfcb1
Fix miscellaneous display warnings for PowerPC & alpha targets
...
and parallel CFI flash driver.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2661 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-14 12:17:09 +00:00
j_mayer
4c9649a967
Alpha architecture emulation core.
...
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2597 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-05 06:58:33 +00:00