Commit graph

5289 commits

Author SHA1 Message Date
aliguori 7c96d46ec2 Let snapshot work with protocols
realpath will horribly mangle a protocol so avoid calling it if the backing
file is a protocol.



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5200 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-12 17:54:13 +00:00
aliguori a145ea5120 uhci: Change default transaction lifetime to 32 frames (Max Krasnyansky)
Transaction lifetime was originally set to 10 frames. That was an arbitrary
number I picked without much thinking :).
I'm changing that to 32 frames because things like interrupt transfers
and such are scheduled at that rate. It seems like 1/32 is accepted as
lowest supported rate. OHCI, for example, defines exactly 32 interrupt
heads.

While testing USB webcam under XP I noticed that interrupt transactions were
being canceled and then resubmitted on a regular basis, which works but is a
waste of CPU cycles. This change fixes that.
All other devices I have are not affected.

Signed-off-by: Max Krasnyansky <maxk@kernel.org>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5199 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-11 19:42:00 +00:00
blueswir1 c5fdf07b80 Enable gcc flag -Wendif-labels
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5198 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-11 18:16:02 +00:00
aliguori a3392f9b10 Only build compatfd when using AIO and make sure to always init AIO
OpenBSD doesn't use AIO so don't try to build compatfd when not using AIO.

Also make sure to call qemu_aio_init() from bdrv_init.  Everything that uses
bdrv calls bdrv_init so it makes sense to init aio from there instead of
in every single tool.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5197 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-11 18:00:19 +00:00
blueswir1 5068cbd9e9 Write zeros to high bits of y, based on patch by Vince Weaver
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5196 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-11 16:01:02 +00:00
aliguori 2c41a5f9e3 Make sure to read siginfo from signalfd
Otherwise, we'll idle at 100% cpu.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5195 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-11 14:32:27 +00:00
aliguori da3d9c5b46 Fix the build on non-Linux systems
It turns out, we're never reading from the signalfd() which is causing it to
remain readable forever.  I'll fix this up but I thought I'd commit this fix
in the interim.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5194 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-11 14:18:56 +00:00
blueswir1 d84763bc17 Convert rest of ops using float32 to TCG, remove FT0 and FT1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5193 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-10 20:09:22 +00:00
blueswir1 c5d04e99f3 Partially convert float128 conversion ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5192 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-10 20:00:18 +00:00
blueswir1 e2ea21b396 Convert basic 64 bit VIS ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5191 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-10 19:57:35 +00:00
blueswir1 1d01299d29 Convert basic 32 bit VIS ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5190 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-10 19:57:13 +00:00
blueswir1 714547bbc7 Convert basic float32 ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5189 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-10 19:54:51 +00:00
aliguori bcdf9b4d16 Add missing files from previous commit.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5188 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-10 18:18:38 +00:00
aliguori baf35cb902 Use signalfd() to work around signal/select race
This patch introduces signalfd() to work around the signal/select race in
checking for AIO completions.  For platforms that don't support signalfd(), we
emulate it with threads.

There was a long discussion about this approach.  I don't believe there are any
fundamental problems with this approach and I believe eliminating the use of
signals is a good thing.

I've tested Windows and Linux using Windows and Linux guests.  I've also checked
for disk IO performance regressions.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5187 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-10 15:45:19 +00:00
aliguori 279826619d qemu-nbd: remove useless parameter from nbd_negotiate() (Laurent Vivier)
This patch removes "BlockDriverState *bs" from nbd_negotiate() because
it is not used.

Signed-off-by: Laurent Vivier <Laurent.Vivier@bull.fr>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5186 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-10 15:23:19 +00:00
blueswir1 3a3b925d47 Implement ldxfsr/stxfsr, fix ld(x)fsr masks, convert to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5185 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-09 19:02:49 +00:00
blueswir1 6f9e38017c Add missing "static"
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5184 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-09 18:56:59 +00:00
aliguori ef14667bfa Add gitignore file
While QEMU officially uses SVN, there are a number of unofficial git
repositories that many developers use.  Adding a .gitignore (derived from the
svn:ignore) will make their lives a lot easier.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5183 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-09 17:15:28 +00:00
aliguori c0a04f0e13 Fix up pxe boot (Glauber Costa)
As discussed in
http://lists.gnu.org/archive/html/qemu-devel/2008-08/msg00667.html,
current pxe boot is broken for some use cases. The problem
goes away if we reduce the number of allowed bits in the address space
to 32 (which has the side effect of reducing guest max mem size to 4Gb).

After digging for a while, it turns out that it happens because pxelinux
tries to access address 0x10009e9a6, which does not fit a 32-bit address.
A closer look, however, reveals this access is totally valid: It's just
0x9e9a6 with an add carry.

To avoid this, this patch casts the address passed to the POPL macro to
a 32-bit value. This is also done, although just theorectically, for
PUSHL too.

Signed-off-by: Glauber Costa <glommer@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Reported-by: Chris Lalancette <clalance@redhat.com>
CC: Eduardo Habkost <ehabkost@redhat.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5182 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-09 14:49:02 +00:00
aurel32 c690524ec1 alpha: only print debug information to the log file
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5181 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-07 21:00:01 +00:00
pbrook 733fef0e40 TCG: Use x86-64 zero extension instructions.
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5180 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-07 18:07:39 +00:00
pbrook b6d17150af Implement TCG sign extension ops for x86-64.
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5179 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-07 17:45:15 +00:00
pbrook 4a7f0e0655 Fix libvdeplug link test.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5178 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-07 16:42:53 +00:00
blueswir1 510aba20f0 Fix a typo in fpsub32
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5177 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-06 17:54:01 +00:00
blueswir1 255e1fcb5a Convert most env fields to TCG registers
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5176 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-06 17:51:43 +00:00
blueswir1 47ad35f16a Silence gcc warning about constant overflow
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5175 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-06 17:50:16 +00:00
blueswir1 5f9981c71d Enable gcc flag -Wundef
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5174 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-06 17:49:06 +00:00
blueswir1 eb38c52c2a Fix most warnings that would be caused by gcc flag -Wundef
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5173 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-06 17:47:39 +00:00
aurel32 5bfd5521ff Some little fixes on QEMU
- some vectors can be declared as "const"
- test on CONFIG_VNC_TLS is done for two times while just one is enough.

(Carlo Bramini)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5172 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-06 16:31:30 +00:00
aurel32 29d26d20e5 fix alpha cmovxx instruction
The CMOV instruction is defined by the alpha manual as:

CMOVxx Ra.rq,Rb.rq,Rc.wq !Operate format
CMOVxx Ra.rq,#b.ib,Rc.wq !Operate format

Operation:
IF TEST(Rav, Condition_based_on_Opcode) THEN
Rc ← Rbv

The current qemu behavior inverses Ra and Rb.  This is fixed by this
patch.

Signed-off-by: Tristan Gingold <gingold@adacore.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5171 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-05 19:07:53 +00:00
edgar_igl 980f8a0b39 CRIS: Mask off the cache selection bit after MMU translations.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5170 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-05 17:17:55 +00:00
aurel32 00dbbb03b6 Revert "TCG: enable debug"
This reverts commit 5166, commited by error.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5169 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-05 14:22:24 +00:00
aurel32 7c417963f7 ppc: Convert op_subf to TCG
Replace op_subf with tcg_gen_sub_tl.

Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5168 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-05 14:19:51 +00:00
aurel32 39dd32eed2 ppc: Convert op_add, op_addi to TCG
Replace op_add with tcg_gen_add_tl and op_addi with tcg_gen_addi_tl.

Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5167 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-05 14:19:43 +00:00
aurel32 b24a39fab0 TCG: enable debug
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5166 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-05 14:19:35 +00:00
aurel32 cdcf4e51aa TCG fixes for target-cris
This patch fixes TCG errors reported on the CRIS target when TCG_DEBUG
is enabled.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Acked-by: Edgar E. Iglesias <edgar@axis.com>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5165 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-05 14:19:27 +00:00
aurel32 2fdbad255e TCG fixes for target-mips
This patch fixes TCG errors reported on the MIPS target when TCG_DEBUG
is enabled.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Acked-by: Thiemo Seufer <ths@networkno.de>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5164 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-05 14:19:17 +00:00
pbrook 9507fb52e2 Fix swapped mvz/mvs instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5163 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-05 12:33:31 +00:00
aurel32 489251fa54 ppc: replace op_set_FT0 with tcg_gen_movi_i64
Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5162 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04 20:34:31 +00:00
aurel32 59df7f62a9 alpha: add target-alpha/helper.h (missing from commit r5150)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5161 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04 20:24:14 +00:00
aurel32 bd568f1849 ppc: Convert nip moves to TCG
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5160 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04 18:06:03 +00:00
aurel32 d38ff48941 ppc: remove unused code
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5159 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04 17:16:41 +00:00
aurel32 47e4661cc4 ppc: Convert CRF moves to TCG
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5158 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04 17:06:47 +00:00
aurel32 ec1ac72d9c ppc: fix fpr TCG registers creation
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5157 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04 15:49:12 +00:00
aurel32 a5e26afa61 ppc: Convert FPR moves to TCG
Replace op_{load,store}_fpr with tcg_gen_mov_i64.
Introduce i64 TCG variables cpu_fpr[0..31] and cpu_FT[0..2].

This obsoletes op_template.h for REG > 7.

Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5156 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04 14:43:54 +00:00
aurel32 1d54269590 ppc: Convert Altivec register moves to TCG
Replace op_{load,store}_avr with helpers gen_{load,store}_avr.
Introduce two sets of i64 TCG variables, cpu_avr{h,l}[0..31], and
cpu_AVR{h,l}[0..2].

Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5155 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04 14:43:45 +00:00
aurel32 bd7d9a6d7b ppc: cleanup register types
- use target_ulong for gpr and dyngen registers
- remove ppc_gpr_t type
- define 64-bit dyngen registers for GPE register on 32-bit targets

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5154 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04 05:26:09 +00:00
aurel32 f78fb44e82 ppc: Convert GPR moves to TCG
Replace op_load_gpr_{T0,T1,T2} and op_store_{T0,T1,T2} with tcg_gen_mov_tl.
Introduce TCG variables cpu_gpr[0..31].

For the SPE extension, assure that ppc_gpr_t is only uint64_t for ppc64.
Introduce TCG variables cpu_gprh[0..31] for upper 32 bits on ppc and helpers
gen_{load,store}_gpr64. Based on suggestions by Aurelien, Thiemo and Blue.

Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5153 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04 05:25:47 +00:00
aurel32 4f821e1757 alpha: convert a few more instructions to TCG
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5152 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04 04:36:20 +00:00
aurel32 3761035f2c alpha: directly access ir registers
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5151 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04 04:36:00 +00:00