Commit graph

356 commits

Author SHA1 Message Date
Richard Henderson fb7729e2d0 target-mips: Always evaluate debugging macro arguments
this will prevent some of the compilation errors with debugging
enabled from creeping back in.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-19 21:40:47 +02:00
Richard Henderson 9fa7748873 target-mips: Fix MIPS_DEBUG.
The macro uses the DisasContext.  Pass it around as needed.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Acked-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-19 21:40:47 +02:00
Richard Henderson e1050a7637 target-mips: Set opn in gen_ldst_multiple.
Used by MIPS_DEBUG, when enabled.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Acked-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-19 21:40:47 +02:00
Blue Swirl 895c2d0435 target-mips: switch to AREG0 free mode
Add an explicit CPUState parameter instead of relying on AREG0
and switch to AREG0 free mode.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Acked-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-15 17:51:13 +00:00
Maciej W. Rozycki 03e6e50177 MIPS/user: Fix reset CPU state initialization
This change updates the CPU reset sequence to use a common piece of code
that figures out CPU state flags, fixing the problem with MIPS_HFLAG_COP1X
not being set where applicable that causes floating-point MADD family
instructions (and other instructions from the MIPS IV FP subset) to trap.

 As compute_hflags is now shared between op_helper.c and translate.c, the
function is now moved to a common header.  There are no changes to this
function.

 The problem was seen with the 24Kf MIPS32r2 processor in user emulation.
The new approach prevents system and user emulation from diverging -- all
the hflags state is initialized in one place now.

Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-08 01:37:23 +02:00
Eric Johnson 36c6711bbe target-mips: allow microMIPS SWP and SDP to have RD equal to BASE
The microMIPS SWP and SDP instructions do not modify GPRs.  So their
behavior is well defined when RD equals BASE.  The MIPS Architecture
Verification Programs (AVPs) check that they work as expected.  This
is required for AVPs to pass.

Signed-off-by: Eric Johnson <ericj@mips.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-08-27 22:18:02 +02:00
Eric Johnson 2e15497c5b target-mips: add privilege level check to several Cop0 instructions
The MIPS Architecture Verification Programs (AVPs) check privileged
instructions for the required privilege level.  These changes are needed
to pass the AVP suite.

Signed-off-by: Eric Johnson <ericj@mips.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-08-27 22:17:59 +02:00
Richard Henderson b316728836 mips-linux-user: Always support rdhwr.
The kernel will emulate this instruction if it's not supported
natively.  This insn is used for TLS, among other things, and
so is required by modern glibc.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Cc: Riku Voipio <riku.voipio@iki.fi>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-08-27 12:17:40 +02:00
Richard Henderson 0516867450 target-mips: Streamline indexed cp1 memory addressing.
We've already eliminated both base and index being zero.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-08-27 12:17:39 +02:00
Richard Sandiford 13d24f4972 Fix order of CVT.PS.S operands
The FS input to CVT.PS.S is the high half and FT is the low half.
tcg_gen_concat_i32_i64 takes the low half first, so the operands
were in the wrong order.

Signed-off-by: Richard Sandiford <rdsandiford@googlemail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-08-27 12:03:18 +02:00
Richard Sandiford d22d728987 Fix operands of RECIP2.S and RECIP2.PS
Read the second input operand of RECIP2.S and RECIP2.PS from FT rather
than FD.  RECIP2.D is already correct.

Signed-off-by: Richard Sandiford <rdsandiford@googlemail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-08-27 12:03:17 +02:00
Meador Inge 94159135cb target-mips: Enable access to required RDHWR hardware registers
While running in the usermode emulator all of the required*
MIPS32r2 RDHWR hardware registers should be accessible (the
Linux kernel enables access to these same registers).  Note
that these registers are still enabled when the MIPS ISA is
not release 2.  This is OK since the Linux kernel emulates
access to them when they are not available in hardware.

* There is also the ULR register which is only recommended
  for full release 2 compliance.  Incidentally, accessing
  this register in the current implementation works fine
  without flipping its access bit.

Signed-off-by: Meador Inge <meadori@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-08-23 17:21:05 +02:00
Nathan Froyd f1cb0951c5 MIPS: Correct FCR0 initialization
This change addresses a problem where QEMU incorrectly traps on
floating-point MADD group instructions with SIGILL, at least while
emulating MIPS32r2 processors.  These instructions use the COP1X major
opcode and include ones like:

	madd.d	$f2,$f4,$f2,$f6

 Here's Nathan's original analysis of the problem:

"QEMU essentially does:

  d = find_cpu (cpu_string)	// get CPU definition
  fpu_init (env, d)		// initialize fpu state (init FCR0, basically)
  cpu_reset (env)

...and the cpu_reset call clears all interesting state that fpu_init
setup, then proceeds to reinitialize all the CP0 registers...but not
FCR0."

 I have verified this change with system emulation running the GDB test
suite for the mips-sde-elf target (o32, big endian, 24Kf CPU emulated),
there were 55 progressions and no regressions.

Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-08-09 18:36:19 +00:00
Andreas Färber 30bf942d8c target-mips: Let cpu_mips_init() return MIPSCPU
Turn cpu_init macro into a static inline function returning CPUMIPSState
for backwards compatibility.

Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-06-04 23:00:43 +02:00
Andreas Färber 3bd4122ef6 target-mips: Use cpu_reset() in cpu_mips_init()
Commit 0f71a7095d (target-mips: QOM'ify
CPU) hooked up cpu_state_reset() to CPUClass::reset(). Dropping the
introduction of subclasses for 1.1, due to mips_def_t the reset code
could not be QOM'ified yet, i.e. cpu_state_reset() will not forward to
CPUClass::reset().

Update cpu_mips_init() with cpu_reset() nontheless, indirectly calling
cpu_state_reset(), so that generic code can be converted to call
cpu_reset().

Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-06-04 23:00:43 +02:00
Richard Sandiford d7f66b52de mips: Fix BC1ANY[24]F instructions
There's some dodgy application of De Morgan's law in the emulation
of the MIPS BC1ANY[24]F instructions: they end up branching only
if all CCs are false, rather than if one CC is.

Tested on mips64-linux-gnu, where it fixes the GCC MIPS3D tests.

Signed-off-by: Richard Sandiford <rdsandiford@googlemail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-05-19 15:51:44 +00:00
Andreas Färber 5b0c40f746 target-mips: Start QOM'ifying CPU init
Move code not dependent on mips_def_t from cpu_mips_init() into a
QOM initfn, as a start.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2012-04-30 11:32:13 +02:00
Andreas Färber 0f71a7095d target-mips: QOM'ify CPU
Embed CPUMIPSState as first member of QOM MIPSCPU.

Let CPUClass::reset() call cpu_state_reset() for now.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2012-04-30 11:32:13 +02:00
Andreas Färber 7db13fae2c target-mips: Don't overuse CPUState
Scripted conversion:
  sed -i "s/CPUState/CPUMIPSState/g" target-mips/*.[hc]
  sed -i "s/#define CPUMIPSState/#define CPUState/" target-mips/cpu.h

Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Anthony Liguori <aliguori@us.ibm.com>
2012-03-14 22:20:25 +01:00
Andreas Färber 1bba0dc932 Rename cpu_reset() to cpu_state_reset()
Frees the identifier cpu_reset for QOM CPUs (manual rename).

Don't hide the parameter type behind explicit casts, use static
functions with strongly typed argument to indirect.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
2012-03-14 22:20:24 +01:00
Stefan Weil 0056c093b6 target-mips: Clean includes
Remove some include statements which are not needed.

Cc: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Stefan Weil <sw@weilnetz.de>
2012-02-28 22:33:42 +01:00
Edgar E. Iglesias 9e56e75624 mips: Initialize MT state at reset
Only TC0 on VPE0 is active after reset. All other VPEs and
TCs start in sleep.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-09-06 11:09:39 +02:00
Edgar E. Iglesias 5a25ce9487 mips: Hook in more reg accesses via mttr/mftr
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-09-06 11:09:38 +02:00
Anthony Liguori 7267c0947d Use glib memory allocation and free functions
qemu_malloc/qemu_free no longer exist after this commit.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-08-20 23:01:08 -05:00
Blue Swirl 2b41f10e18 Remove exec-all.h include directives
Most exec-all.h include directives are now useless, remove them.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26 18:25:35 +00:00
Stefan Weil e87b7cb0f0 Remove unused function parameters from gen_pc_load and rename the function
Function gen_pc_load was introduced in commit
d2856f1ad4.
The only reason for parameter searched_pc was
a debug statement in target-i386/translate.c.

Parameter puc was needed by target-sparc until
commit d7da2a1040.

Remove searched_pc from the debug statement and remove both
parameters from the parameter list of gen_pc_load.

As the function name gen_pc_load was also misleading,
it is now called restore_state_to_opc. This new name
was suggested by Peter Maydell, thanks.

v2: Remove last parameter, too, and rename the function.

v3: Fix [] typo in target-arm/translate.c.
    Fix wrong SHA1 object name in commit message (copy+paste error).

Cc: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
2011-04-20 10:33:59 +02:00
Stefan Weil 4b4a72e556 Fix conversions from pointer to tcg_target_long
tcg_gen_exit_tb takes a parameter of type tcg_target_long,
so the type casts of pointer to long should be replaced by
type casts of pointer to tcg_target_long (suggested by Blue Swirl).

These changes are needed for build environments where
sizeof(long) != sizeof(void *), especially for w64.

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-10 00:45:16 +02:00
Aurelien Jarno b835e919f0 target-mips: fix save_cpu_state() calls
The rule is:
- don't save PC if the exception is only triggered by softmmu.
- save PC if the exception can be triggered by an helper.

Fix a 64-bit kernel crash when loading modules.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-24 20:52:04 +01:00
Edgar E. Iglesias 5580722456 mips: Break TBs after mfc0_count
Break the TB after reading the count register. This makes it
possible to take timer interrupts immediately after a read of
a possibly expired timer.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-01-18 12:32:46 +01:00
Nathan Froyd 9ed5726c04 target-mips: fix translation of MT instructions
The translation of dmt/emt/dvpe/evpe was doing the moral equivalent of:

  int x;
  ...		/* no initialization of x */
  x = f (x);

which confused later bits of TCG rather badly, leading to crashes.

Fix the helpers to only return results (those instructions have no
inputs), and fix the translation code accordingly.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-22 11:14:10 +01:00
Stefan Weil 9a78eead0c target-xxx: Use fprintf_function (format checking)
fprintf_function uses format checking with GCC_FMT_ATTR.

Format errors were fixed in
* target-i386/helper.c
* target-mips/translate.c
* target-ppc/translate.c

Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-10-30 08:01:59 +00:00
Blue Swirl 2abf314ddd mips: avoid write only variables
Compiling with GCC 4.6.0 20100925 produced a lot of warnings like:
/src/qemu/target-mips/translate.c: In function 'gen_ld':
/src/qemu/target-mips/translate.c:1039:17: error: variable 'opn' set but not used [-Werror=unused-but-set-variable]

Fix by adding a dummy cast so that the variable is not unused.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-10-13 18:43:21 +00:00
Hervé Poussineau 671b0f368b Correctly identify multiple cpus in SMP systems
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-07-31 17:14:52 +02:00
Aurelien Jarno 5dc5d9f055 mips: more fixes to the MIPS interrupt glue logic
Commit 36388314fe moved most of the
interrupt logic to cpu-exec.c. Remove the remaining useless code
and fix software interrupts.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Acked-by: Edgar E. Iglesias <edgar@axis.com>
Tested-by: Edgar E. Iglesias <edgar@axis.com>
2010-07-25 16:54:02 +02:00
Aurelien Jarno 161f85e6b1 target-mips: add loongson 2E & 2F integer instructions
This patch adds support for loongson 2E & 2F instructions. They are the
same instructions, but differ by the opcode encoding.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-07-11 10:24:31 +02:00
Aurelien Jarno afa88c3ae5 target-mips: add Loongson support prefetch
Loongson CPU uses a load to zero register for prefetch.
Emulate it as a NOP.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-07-01 23:45:28 +02:00
Aurelien Jarno 5c13fdfd03 target-mips: split load and store
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-07-01 07:48:17 +02:00
Aurelien Jarno 6fbab86925 target-mips: fix DINSU instruction
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-30 20:00:31 +02:00
Aurelien Jarno aa8f40090a target-mips: enable movn/movz on loongson 2E & 2F
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-29 23:26:34 +02:00
Stefan Weil 3308759844 target-mips: Fix compilation
TCGv t1 needs tcg_temp_free instead of tcg_temp_free_i32.

Cc: Nathan Froyd <froydnj@codesourcery.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09 23:37:36 +02:00
Nathan Froyd 3c824109da target-mips: microMIPS ASE support
Add instruction decoding for the microMIPS ASE.  All we do is decode and
then forward to the existing gen_* routines.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09 16:10:50 +02:00
Nathan Froyd 620e48f663 target-mips: mips16 cleanups
Change code handling mips16-specific branches to use ISA-neutral special
opcodes.  Since there are several places where the delay slot
requirements for microMIPS branches differ from mips16 branches, using
opcodes is easier than checking hflags, then checking mips16
vs. microMIPS.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09 16:10:50 +02:00
Nathan Froyd 8153667c71 target-mips: refactor c{, abs}.cond.fmt insns
Move all knowledge about coprocessor-checking and register numbering
into the gen_cmp* helper functions.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09 16:10:50 +02:00
Aurelien Jarno e459440a89 target-mips: move FP FMT comments closer to the definitions
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09 16:10:50 +02:00
Nathan Froyd bf4120adaa target-mips: define constants for magic numbers
Add FMT_* constants for the floating-point format field in opcodes and
tweak a few places to use them.  Add enums for various invocations of
FOP and tweak gen_farith and its lone caller accordingly.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09 16:10:50 +02:00
Nathan Froyd 26ebe46848 target-mips: break out [ls][wd]c1 and rdhwr insn generation
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Acked-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-08 19:15:08 +02:00
Richard Henderson 564856bb97 target-mips: Remove duplicate CPU log.
Logging for -d cpu is done in generic code.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-05 12:20:05 +02:00
Stefan Weil 2a5612e6a3 target-mips: Fix format specifiers for fpu_fprintf
In the previous patch which introduced fprintf_function to
allow parameter checking by gcc some compiler warnings
remained unfixed.

These warnings are fixed here.

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-09 21:53:23 +02:00
Stefan Weil a7200c9f98 target-mips: Fix one more format specifier for cpu_fprintf
env->bcond must be printed using TARGET_FMT_ld.

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-08 21:46:57 +02:00
Paolo Bonzini 1a7ff92218 remove TARGET_* defines from translate-all.c
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-08 21:34:12 +02:00