Thomas Huth
fcf5ef2ab5
Move target-* CPU file into a target/ folder
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We've currently got 18 architectures in QEMU, and thus 18 target-xxx
folders in the root folder of the QEMU source tree. More architectures
(e.g. RISC-V, AVR) are likely to be included soon, too, so the main
folder of the QEMU sources slowly gets quite overcrowded with the
target-xxx folders.
To disburden the main folder a little bit, let's move the target-xxx
folders into a dedicated target/ folder, so that target-xxx/ simply
becomes target/xxx/ instead.
Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part]
Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part]
Acked-by: Michael Walle <michael@walle.cc> [lm32 part]
Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part]
Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part]
Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part]
Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part]
Acked-by: Richard Henderson <rth@twiddle.net> [alpha part]
Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part]
Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part]
Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [crisµblaze part]
Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part]
Signed-off-by: Thomas Huth <thuth@redhat.com>
2016-12-20 21:52:12 +01:00
Jia Liu
b30706dda7
target-mips: Change TODO file
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Change DSP r1 & DSP r2 into microMIPS DSP encodings in TODO file.
Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31 21:37:24 +01:00
Stefan Weil
6576b74b0b
Replace Qemu by QEMU in internal documentation
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The official spelling is QEMU.
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-07 13:58:25 +00:00
Nathan Froyd
9da53be7ea
target-mips: add copyright notice for mips16 work
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Also cross off mips16 ASE in TODO.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13 20:20:20 +01:00
ths
f01be15458
Move the active FPU registers into env again, and use more TCG registers
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to access them.
Signed-off-by: Thiemo Seufer <ths@networkno.de>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5252 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-18 11:57:27 +00:00
ths
ebbd0ffddd
Clarify some TODO items.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4789 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-24 22:04:41 +00:00
ths
2681b45add
Update TODO list.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4735 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-11 20:58:36 +00:00
ths
bec19c0932
Mention missing CPU save/restore.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4381 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-07 15:39:12 +00:00
ths
0300e3faf6
MIPS TODO: mention unimplemented system controllers.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3830 c046a42c-6fe2-441c-8c8c-71466251a162
2007-12-17 03:53:42 +00:00
ths
bbbe9b8822
Update MIPS TODO. The mipsnet failure is caused by a kernel bug.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3829 c046a42c-6fe2-441c-8c8c-71466251a162
2007-12-17 03:50:28 +00:00
ths
c7890fc209
Update TODO.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3402 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-17 13:43:58 +00:00
ths
d0f48074db
Update TODO.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3383 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-13 19:00:52 +00:00
ths
540635ba65
Code provision for n32/n64 mips userland emulation. Not functional yet.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3284 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-30 01:58:33 +00:00
ths
a09d88b86a
Update TODO.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3278 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-30 00:45:51 +00:00
ths
475d91106d
Update TODO list.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3057 c046a42c-6fe2-441c-8c8c-71466251a162
2007-07-11 10:25:04 +00:00
ths
1e3d0552f5
Update some comments, 64bit FPU support is functional regardless of
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funny non-standard fcr0 bits on earlier CPUs.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2919 c046a42c-6fe2-441c-8c8c-71466251a162
2007-06-01 21:57:32 +00:00
ths
c13af1ef6c
Update TODO.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2911 c046a42c-6fe2-441c-8c8c-71466251a162
2007-06-01 15:18:04 +00:00
ths
5a5012ecbd
MIPS 64-bit FPU support, plus some collateral bugfixes in the
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conditional branch handling.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2779 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-07 13:55:33 +00:00
ths
8b4af70527
Update TODO.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2778 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-07 12:52:18 +00:00
ths
509b8ab2cc
Update TODO.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2739 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-28 21:44:04 +00:00
ths
7246bb21ba
Update mips TODO.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2549 c046a42c-6fe2-441c-8c8c-71466251a162
2007-03-30 18:56:19 +00:00
ths
60a9f9ecd9
Note FPU enable/disable issue.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2489 c046a42c-6fe2-441c-8c8c-71466251a162
2007-03-17 15:39:48 +00:00
ths
4a109bfbca
Update MIPS TODO.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2378 c046a42c-6fe2-441c-8c8c-71466251a162
2007-02-02 02:56:33 +00:00
ths
81e1e20979
Update TODO.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2346 c046a42c-6fe2-441c-8c8c-71466251a162
2007-01-22 20:57:17 +00:00
ths
72f341ed1e
TLB address wraparound hopefully fixed now.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2342 c046a42c-6fe2-441c-8c8c-71466251a162
2007-01-21 03:13:58 +00:00
ths
15dcf5aa86
Note more issues.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2335 c046a42c-6fe2-441c-8c8c-71466251a162
2007-01-19 17:56:23 +00:00
ths
2c52c8169a
Keep track of mips related issues.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2325 c046a42c-6fe2-441c-8c8c-71466251a162
2007-01-17 20:03:15 +00:00