When a CDB has been received and is about to be submitted to the SCSI layer via one of the ESP select commands, ensure that do_cmd is set to zero before executing the command. Otherwise a guest executing 2 valid CDBs in quick sequence can invoke the SCSI .transfer_data callback again before do_cmd is set to zero by the callback function triggering an assert at the start of esp_transfer_data(). Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210407195801.685-12-mark.cave-ayland@ilande.co.uk>
1389 lines
36 KiB
C
1389 lines
36 KiB
C
/*
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* QEMU ESP/NCR53C9x emulation
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*
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* Copyright (c) 2005-2006 Fabrice Bellard
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* Copyright (c) 2012 Herve Poussineau
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "hw/irq.h"
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#include "hw/scsi/esp.h"
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#include "trace.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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/*
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* On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O),
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* also produced as NCR89C100. See
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* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
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* and
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* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
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*
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* On Macintosh Quadra it is a NCR53C96.
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*/
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static void esp_raise_irq(ESPState *s)
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{
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if (!(s->rregs[ESP_RSTAT] & STAT_INT)) {
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s->rregs[ESP_RSTAT] |= STAT_INT;
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qemu_irq_raise(s->irq);
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trace_esp_raise_irq();
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}
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}
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static void esp_lower_irq(ESPState *s)
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{
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if (s->rregs[ESP_RSTAT] & STAT_INT) {
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s->rregs[ESP_RSTAT] &= ~STAT_INT;
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qemu_irq_lower(s->irq);
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trace_esp_lower_irq();
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}
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}
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static void esp_raise_drq(ESPState *s)
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{
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qemu_irq_raise(s->irq_data);
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trace_esp_raise_drq();
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}
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static void esp_lower_drq(ESPState *s)
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{
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qemu_irq_lower(s->irq_data);
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trace_esp_lower_drq();
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}
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void esp_dma_enable(ESPState *s, int irq, int level)
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{
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if (level) {
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s->dma_enabled = 1;
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trace_esp_dma_enable();
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if (s->dma_cb) {
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s->dma_cb(s);
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s->dma_cb = NULL;
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}
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} else {
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trace_esp_dma_disable();
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s->dma_enabled = 0;
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}
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}
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void esp_request_cancelled(SCSIRequest *req)
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{
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ESPState *s = req->hba_private;
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if (req == s->current_req) {
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scsi_req_unref(s->current_req);
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s->current_req = NULL;
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s->current_dev = NULL;
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s->async_len = 0;
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}
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}
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static void esp_fifo_push(Fifo8 *fifo, uint8_t val)
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{
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if (fifo8_num_used(fifo) == fifo->capacity) {
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trace_esp_error_fifo_overrun();
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return;
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}
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fifo8_push(fifo, val);
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}
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static uint8_t esp_fifo_pop(Fifo8 *fifo)
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{
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if (fifo8_is_empty(fifo)) {
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return 0;
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}
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return fifo8_pop(fifo);
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}
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static uint32_t esp_fifo_pop_buf(Fifo8 *fifo, uint8_t *dest, int maxlen)
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{
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const uint8_t *buf;
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uint32_t n;
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if (maxlen == 0) {
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return 0;
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}
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buf = fifo8_pop_buf(fifo, maxlen, &n);
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if (dest) {
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memcpy(dest, buf, n);
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}
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return n;
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}
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static uint32_t esp_get_tc(ESPState *s)
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{
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uint32_t dmalen;
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dmalen = s->rregs[ESP_TCLO];
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dmalen |= s->rregs[ESP_TCMID] << 8;
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dmalen |= s->rregs[ESP_TCHI] << 16;
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return dmalen;
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}
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static void esp_set_tc(ESPState *s, uint32_t dmalen)
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{
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s->rregs[ESP_TCLO] = dmalen;
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s->rregs[ESP_TCMID] = dmalen >> 8;
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s->rregs[ESP_TCHI] = dmalen >> 16;
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}
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static uint32_t esp_get_stc(ESPState *s)
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{
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uint32_t dmalen;
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dmalen = s->wregs[ESP_TCLO];
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dmalen |= s->wregs[ESP_TCMID] << 8;
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dmalen |= s->wregs[ESP_TCHI] << 16;
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return dmalen;
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}
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static uint8_t esp_pdma_read(ESPState *s)
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{
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uint8_t val;
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if (s->do_cmd) {
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val = esp_fifo_pop(&s->cmdfifo);
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} else {
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val = esp_fifo_pop(&s->fifo);
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}
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return val;
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}
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static void esp_pdma_write(ESPState *s, uint8_t val)
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{
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uint32_t dmalen = esp_get_tc(s);
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if (dmalen == 0) {
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return;
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}
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if (s->do_cmd) {
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esp_fifo_push(&s->cmdfifo, val);
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} else {
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esp_fifo_push(&s->fifo, val);
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}
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dmalen--;
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esp_set_tc(s, dmalen);
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}
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static int esp_select(ESPState *s)
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{
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int target;
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target = s->wregs[ESP_WBUSID] & BUSID_DID;
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s->ti_size = 0;
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fifo8_reset(&s->fifo);
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if (s->current_req) {
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/* Started a new command before the old one finished. Cancel it. */
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scsi_req_cancel(s->current_req);
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}
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s->current_dev = scsi_device_find(&s->bus, 0, target, 0);
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if (!s->current_dev) {
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/* No such drive */
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s->rregs[ESP_RSTAT] = 0;
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s->rregs[ESP_RINTR] |= INTR_DC;
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s->rregs[ESP_RSEQ] = SEQ_0;
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esp_raise_irq(s);
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return -1;
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}
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/*
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* Note that we deliberately don't raise the IRQ here: this will be done
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* either in do_busid_cmd() for DATA OUT transfers or by the deferred
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* IRQ mechanism in esp_transfer_data() for DATA IN transfers
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*/
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s->rregs[ESP_RINTR] |= INTR_FC;
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s->rregs[ESP_RSEQ] = SEQ_CD;
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return 0;
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}
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static uint32_t get_cmd(ESPState *s, uint32_t maxlen)
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{
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uint8_t buf[ESP_CMDFIFO_SZ];
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uint32_t dmalen, n;
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int target;
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target = s->wregs[ESP_WBUSID] & BUSID_DID;
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if (s->dma) {
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dmalen = MIN(esp_get_tc(s), maxlen);
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if (dmalen == 0) {
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return 0;
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}
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if (s->dma_memory_read) {
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s->dma_memory_read(s->dma_opaque, buf, dmalen);
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dmalen = MIN(fifo8_num_free(&s->cmdfifo), dmalen);
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fifo8_push_all(&s->cmdfifo, buf, dmalen);
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} else {
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if (esp_select(s) < 0) {
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fifo8_reset(&s->cmdfifo);
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return -1;
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}
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esp_raise_drq(s);
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fifo8_reset(&s->cmdfifo);
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return 0;
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}
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} else {
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dmalen = MIN(fifo8_num_used(&s->fifo), maxlen);
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if (dmalen == 0) {
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return 0;
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}
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n = esp_fifo_pop_buf(&s->fifo, buf, dmalen);
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if (n >= 3) {
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buf[0] = buf[2] >> 5;
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}
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n = MIN(fifo8_num_free(&s->cmdfifo), n);
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fifo8_push_all(&s->cmdfifo, buf, n);
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}
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trace_esp_get_cmd(dmalen, target);
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if (esp_select(s) < 0) {
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fifo8_reset(&s->cmdfifo);
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return -1;
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}
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return dmalen;
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}
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static void do_busid_cmd(ESPState *s, uint8_t busid)
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{
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uint32_t cmdlen;
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int32_t datalen;
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int lun;
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SCSIDevice *current_lun;
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uint8_t buf[ESP_CMDFIFO_SZ];
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trace_esp_do_busid_cmd(busid);
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lun = busid & 7;
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cmdlen = fifo8_num_used(&s->cmdfifo);
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if (!cmdlen || !s->current_dev) {
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return;
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}
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esp_fifo_pop_buf(&s->cmdfifo, buf, cmdlen);
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current_lun = scsi_device_find(&s->bus, 0, s->current_dev->id, lun);
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s->current_req = scsi_req_new(current_lun, 0, lun, buf, s);
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datalen = scsi_req_enqueue(s->current_req);
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s->ti_size = datalen;
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fifo8_reset(&s->cmdfifo);
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if (datalen != 0) {
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s->rregs[ESP_RSTAT] = STAT_TC;
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s->rregs[ESP_RSEQ] = SEQ_CD;
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s->ti_cmd = 0;
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esp_set_tc(s, 0);
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if (datalen > 0) {
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/*
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* Switch to DATA IN phase but wait until initial data xfer is
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* complete before raising the command completion interrupt
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*/
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s->data_in_ready = false;
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s->rregs[ESP_RSTAT] |= STAT_DI;
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} else {
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s->rregs[ESP_RSTAT] |= STAT_DO;
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s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC;
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esp_raise_irq(s);
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esp_lower_drq(s);
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}
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scsi_req_continue(s->current_req);
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return;
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}
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}
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static void do_cmd(ESPState *s)
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{
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uint8_t busid = esp_fifo_pop(&s->cmdfifo);
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int len;
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s->cmdfifo_cdb_offset--;
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/* Ignore extended messages for now */
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if (s->cmdfifo_cdb_offset) {
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len = MIN(s->cmdfifo_cdb_offset, fifo8_num_used(&s->cmdfifo));
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esp_fifo_pop_buf(&s->cmdfifo, NULL, len);
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s->cmdfifo_cdb_offset = 0;
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}
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do_busid_cmd(s, busid);
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}
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static void satn_pdma_cb(ESPState *s)
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{
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s->do_cmd = 0;
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if (!fifo8_is_empty(&s->cmdfifo)) {
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s->cmdfifo_cdb_offset = 1;
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do_cmd(s);
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}
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}
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static void handle_satn(ESPState *s)
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{
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int32_t cmdlen;
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if (s->dma && !s->dma_enabled) {
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s->dma_cb = handle_satn;
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return;
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}
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s->pdma_cb = satn_pdma_cb;
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cmdlen = get_cmd(s, ESP_CMDFIFO_SZ);
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if (cmdlen > 0) {
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s->cmdfifo_cdb_offset = 1;
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s->do_cmd = 0;
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do_cmd(s);
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} else if (cmdlen == 0) {
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s->do_cmd = 1;
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/* Target present, but no cmd yet - switch to command phase */
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s->rregs[ESP_RSEQ] = SEQ_CD;
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s->rregs[ESP_RSTAT] = STAT_CD;
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}
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}
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static void s_without_satn_pdma_cb(ESPState *s)
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{
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uint32_t len;
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s->do_cmd = 0;
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len = fifo8_num_used(&s->cmdfifo);
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if (len) {
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s->cmdfifo_cdb_offset = 0;
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do_busid_cmd(s, 0);
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}
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}
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static void handle_s_without_atn(ESPState *s)
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{
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int32_t cmdlen;
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if (s->dma && !s->dma_enabled) {
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s->dma_cb = handle_s_without_atn;
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return;
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}
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s->pdma_cb = s_without_satn_pdma_cb;
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cmdlen = get_cmd(s, ESP_CMDFIFO_SZ);
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if (cmdlen > 0) {
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s->cmdfifo_cdb_offset = 0;
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s->do_cmd = 0;
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do_busid_cmd(s, 0);
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} else if (cmdlen == 0) {
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s->do_cmd = 1;
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/* Target present, but no cmd yet - switch to command phase */
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s->rregs[ESP_RSEQ] = SEQ_CD;
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s->rregs[ESP_RSTAT] = STAT_CD;
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}
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}
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static void satn_stop_pdma_cb(ESPState *s)
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{
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s->do_cmd = 0;
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if (!fifo8_is_empty(&s->cmdfifo)) {
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trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo));
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s->do_cmd = 1;
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s->cmdfifo_cdb_offset = 1;
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s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD;
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s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC;
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s->rregs[ESP_RSEQ] = SEQ_CD;
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esp_raise_irq(s);
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}
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}
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static void handle_satn_stop(ESPState *s)
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{
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int32_t cmdlen;
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if (s->dma && !s->dma_enabled) {
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s->dma_cb = handle_satn_stop;
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return;
|
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}
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s->pdma_cb = satn_stop_pdma_cb;
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cmdlen = get_cmd(s, 1);
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if (cmdlen > 0) {
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trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo));
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s->do_cmd = 1;
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s->cmdfifo_cdb_offset = 1;
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s->rregs[ESP_RSTAT] = STAT_MO;
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s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC;
|
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s->rregs[ESP_RSEQ] = SEQ_MO;
|
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esp_raise_irq(s);
|
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} else if (cmdlen == 0) {
|
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s->do_cmd = 1;
|
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/* Target present, switch to message out phase */
|
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s->rregs[ESP_RSEQ] = SEQ_MO;
|
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s->rregs[ESP_RSTAT] = STAT_MO;
|
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}
|
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}
|
|
|
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static void write_response_pdma_cb(ESPState *s)
|
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{
|
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s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST;
|
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s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC;
|
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s->rregs[ESP_RSEQ] = SEQ_CD;
|
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esp_raise_irq(s);
|
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}
|
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|
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static void write_response(ESPState *s)
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{
|
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uint8_t buf[2];
|
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|
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trace_esp_write_response(s->status);
|
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|
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buf[0] = s->status;
|
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buf[1] = 0;
|
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|
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if (s->dma) {
|
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if (s->dma_memory_write) {
|
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s->dma_memory_write(s->dma_opaque, buf, 2);
|
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s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST;
|
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s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC;
|
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s->rregs[ESP_RSEQ] = SEQ_CD;
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} else {
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s->pdma_cb = write_response_pdma_cb;
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esp_raise_drq(s);
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return;
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}
|
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} else {
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fifo8_reset(&s->fifo);
|
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fifo8_push_all(&s->fifo, buf, 2);
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s->rregs[ESP_RFLAGS] = 2;
|
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}
|
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esp_raise_irq(s);
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}
|
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|
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static void esp_dma_done(ESPState *s)
|
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{
|
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s->rregs[ESP_RSTAT] |= STAT_TC;
|
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s->rregs[ESP_RINTR] |= INTR_BS;
|
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s->rregs[ESP_RSEQ] = 0;
|
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s->rregs[ESP_RFLAGS] = 0;
|
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esp_set_tc(s, 0);
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esp_raise_irq(s);
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}
|
|
|
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static void do_dma_pdma_cb(ESPState *s)
|
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{
|
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int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO);
|
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int len;
|
|
uint32_t n;
|
|
|
|
if (s->do_cmd) {
|
|
s->ti_size = 0;
|
|
s->do_cmd = 0;
|
|
do_cmd(s);
|
|
esp_lower_drq(s);
|
|
return;
|
|
}
|
|
|
|
if (!s->current_req) {
|
|
return;
|
|
}
|
|
|
|
if (to_device) {
|
|
/* Copy FIFO data to device */
|
|
len = MIN(s->async_len, ESP_FIFO_SZ);
|
|
len = MIN(len, fifo8_num_used(&s->fifo));
|
|
n = esp_fifo_pop_buf(&s->fifo, s->async_buf, len);
|
|
s->async_buf += n;
|
|
s->async_len -= n;
|
|
s->ti_size += n;
|
|
|
|
if (n < len) {
|
|
/* Unaligned accesses can cause FIFO wraparound */
|
|
len = len - n;
|
|
n = esp_fifo_pop_buf(&s->fifo, s->async_buf, len);
|
|
s->async_buf += n;
|
|
s->async_len -= n;
|
|
s->ti_size += n;
|
|
}
|
|
|
|
if (s->async_len == 0) {
|
|
scsi_req_continue(s->current_req);
|
|
return;
|
|
}
|
|
|
|
if (esp_get_tc(s) == 0) {
|
|
esp_lower_drq(s);
|
|
esp_dma_done(s);
|
|
}
|
|
|
|
return;
|
|
} else {
|
|
if (s->async_len == 0) {
|
|
/* Defer until the scsi layer has completed */
|
|
scsi_req_continue(s->current_req);
|
|
s->data_in_ready = false;
|
|
return;
|
|
}
|
|
|
|
if (esp_get_tc(s) != 0) {
|
|
/* Copy device data to FIFO */
|
|
len = MIN(s->async_len, esp_get_tc(s));
|
|
len = MIN(len, fifo8_num_free(&s->fifo));
|
|
fifo8_push_all(&s->fifo, s->async_buf, len);
|
|
s->async_buf += len;
|
|
s->async_len -= len;
|
|
s->ti_size -= len;
|
|
esp_set_tc(s, esp_get_tc(s) - len);
|
|
|
|
if (esp_get_tc(s) == 0) {
|
|
/* Indicate transfer to FIFO is complete */
|
|
s->rregs[ESP_RSTAT] |= STAT_TC;
|
|
}
|
|
return;
|
|
}
|
|
|
|
/* Partially filled a scsi buffer. Complete immediately. */
|
|
esp_lower_drq(s);
|
|
esp_dma_done(s);
|
|
}
|
|
}
|
|
|
|
static void esp_do_dma(ESPState *s)
|
|
{
|
|
uint32_t len, cmdlen;
|
|
int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO);
|
|
uint8_t buf[ESP_CMDFIFO_SZ];
|
|
|
|
len = esp_get_tc(s);
|
|
if (s->do_cmd) {
|
|
/*
|
|
* handle_ti_cmd() case: esp_do_dma() is called only from
|
|
* handle_ti_cmd() with do_cmd != NULL (see the assert())
|
|
*/
|
|
cmdlen = fifo8_num_used(&s->cmdfifo);
|
|
trace_esp_do_dma(cmdlen, len);
|
|
if (s->dma_memory_read) {
|
|
len = MIN(len, fifo8_num_free(&s->cmdfifo));
|
|
s->dma_memory_read(s->dma_opaque, buf, len);
|
|
fifo8_push_all(&s->cmdfifo, buf, len);
|
|
} else {
|
|
s->pdma_cb = do_dma_pdma_cb;
|
|
esp_raise_drq(s);
|
|
return;
|
|
}
|
|
trace_esp_handle_ti_cmd(cmdlen);
|
|
s->ti_size = 0;
|
|
if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) {
|
|
/* No command received */
|
|
if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) {
|
|
return;
|
|
}
|
|
|
|
/* Command has been received */
|
|
s->do_cmd = 0;
|
|
do_cmd(s);
|
|
} else {
|
|
/*
|
|
* Extra message out bytes received: update cmdfifo_cdb_offset
|
|
* and then switch to commmand phase
|
|
*/
|
|
s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo);
|
|
s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD;
|
|
s->rregs[ESP_RSEQ] = SEQ_CD;
|
|
s->rregs[ESP_RINTR] |= INTR_BS;
|
|
esp_raise_irq(s);
|
|
}
|
|
return;
|
|
}
|
|
if (!s->current_req) {
|
|
return;
|
|
}
|
|
if (s->async_len == 0) {
|
|
/* Defer until data is available. */
|
|
return;
|
|
}
|
|
if (len > s->async_len) {
|
|
len = s->async_len;
|
|
}
|
|
if (to_device) {
|
|
if (s->dma_memory_read) {
|
|
s->dma_memory_read(s->dma_opaque, s->async_buf, len);
|
|
} else {
|
|
s->pdma_cb = do_dma_pdma_cb;
|
|
esp_raise_drq(s);
|
|
return;
|
|
}
|
|
} else {
|
|
if (s->dma_memory_write) {
|
|
s->dma_memory_write(s->dma_opaque, s->async_buf, len);
|
|
} else {
|
|
/* Adjust TC for any leftover data in the FIFO */
|
|
if (!fifo8_is_empty(&s->fifo)) {
|
|
esp_set_tc(s, esp_get_tc(s) - fifo8_num_used(&s->fifo));
|
|
}
|
|
|
|
/* Copy device data to FIFO */
|
|
len = MIN(len, fifo8_num_free(&s->fifo));
|
|
fifo8_push_all(&s->fifo, s->async_buf, len);
|
|
s->async_buf += len;
|
|
s->async_len -= len;
|
|
s->ti_size -= len;
|
|
|
|
/*
|
|
* MacOS toolbox uses a TI length of 16 bytes for all commands, so
|
|
* commands shorter than this must be padded accordingly
|
|
*/
|
|
if (len < esp_get_tc(s) && esp_get_tc(s) <= ESP_FIFO_SZ) {
|
|
while (fifo8_num_used(&s->fifo) < ESP_FIFO_SZ) {
|
|
esp_fifo_push(&s->fifo, 0);
|
|
len++;
|
|
}
|
|
}
|
|
|
|
esp_set_tc(s, esp_get_tc(s) - len);
|
|
s->pdma_cb = do_dma_pdma_cb;
|
|
esp_raise_drq(s);
|
|
|
|
/* Indicate transfer to FIFO is complete */
|
|
s->rregs[ESP_RSTAT] |= STAT_TC;
|
|
return;
|
|
}
|
|
}
|
|
esp_set_tc(s, esp_get_tc(s) - len);
|
|
s->async_buf += len;
|
|
s->async_len -= len;
|
|
if (to_device) {
|
|
s->ti_size += len;
|
|
} else {
|
|
s->ti_size -= len;
|
|
}
|
|
if (s->async_len == 0) {
|
|
scsi_req_continue(s->current_req);
|
|
/*
|
|
* If there is still data to be read from the device then
|
|
* complete the DMA operation immediately. Otherwise defer
|
|
* until the scsi layer has completed.
|
|
*/
|
|
if (to_device || esp_get_tc(s) != 0 || s->ti_size == 0) {
|
|
return;
|
|
}
|
|
}
|
|
|
|
/* Partially filled a scsi buffer. Complete immediately. */
|
|
esp_dma_done(s);
|
|
esp_lower_drq(s);
|
|
}
|
|
|
|
static void esp_do_nodma(ESPState *s)
|
|
{
|
|
int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO);
|
|
uint32_t cmdlen;
|
|
int len;
|
|
|
|
if (s->do_cmd) {
|
|
cmdlen = fifo8_num_used(&s->cmdfifo);
|
|
trace_esp_handle_ti_cmd(cmdlen);
|
|
s->ti_size = 0;
|
|
if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) {
|
|
/* No command received */
|
|
if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) {
|
|
return;
|
|
}
|
|
|
|
/* Command has been received */
|
|
s->do_cmd = 0;
|
|
do_cmd(s);
|
|
} else {
|
|
/*
|
|
* Extra message out bytes received: update cmdfifo_cdb_offset
|
|
* and then switch to commmand phase
|
|
*/
|
|
s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo);
|
|
s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD;
|
|
s->rregs[ESP_RSEQ] = SEQ_CD;
|
|
s->rregs[ESP_RINTR] |= INTR_BS;
|
|
esp_raise_irq(s);
|
|
}
|
|
return;
|
|
}
|
|
|
|
if (!s->current_req) {
|
|
return;
|
|
}
|
|
|
|
if (s->async_len == 0) {
|
|
/* Defer until data is available. */
|
|
return;
|
|
}
|
|
|
|
if (to_device) {
|
|
len = MIN(fifo8_num_used(&s->fifo), ESP_FIFO_SZ);
|
|
esp_fifo_pop_buf(&s->fifo, s->async_buf, len);
|
|
s->async_buf += len;
|
|
s->async_len -= len;
|
|
s->ti_size += len;
|
|
} else {
|
|
len = MIN(s->ti_size, s->async_len);
|
|
len = MIN(len, fifo8_num_free(&s->fifo));
|
|
fifo8_push_all(&s->fifo, s->async_buf, len);
|
|
s->async_buf += len;
|
|
s->async_len -= len;
|
|
s->ti_size -= len;
|
|
}
|
|
|
|
if (s->async_len == 0) {
|
|
scsi_req_continue(s->current_req);
|
|
|
|
if (to_device || s->ti_size == 0) {
|
|
return;
|
|
}
|
|
}
|
|
|
|
s->rregs[ESP_RINTR] |= INTR_BS;
|
|
esp_raise_irq(s);
|
|
}
|
|
|
|
void esp_command_complete(SCSIRequest *req, size_t resid)
|
|
{
|
|
ESPState *s = req->hba_private;
|
|
|
|
trace_esp_command_complete();
|
|
if (s->ti_size != 0) {
|
|
trace_esp_command_complete_unexpected();
|
|
}
|
|
s->ti_size = 0;
|
|
s->async_len = 0;
|
|
if (req->status) {
|
|
trace_esp_command_complete_fail();
|
|
}
|
|
s->status = req->status;
|
|
s->rregs[ESP_RSTAT] = STAT_ST;
|
|
esp_dma_done(s);
|
|
esp_lower_drq(s);
|
|
if (s->current_req) {
|
|
scsi_req_unref(s->current_req);
|
|
s->current_req = NULL;
|
|
s->current_dev = NULL;
|
|
}
|
|
}
|
|
|
|
void esp_transfer_data(SCSIRequest *req, uint32_t len)
|
|
{
|
|
ESPState *s = req->hba_private;
|
|
int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO);
|
|
uint32_t dmalen = esp_get_tc(s);
|
|
|
|
assert(!s->do_cmd);
|
|
trace_esp_transfer_data(dmalen, s->ti_size);
|
|
s->async_len = len;
|
|
s->async_buf = scsi_req_get_buf(req);
|
|
|
|
if (!to_device && !s->data_in_ready) {
|
|
/*
|
|
* Initial incoming data xfer is complete so raise command
|
|
* completion interrupt
|
|
*/
|
|
s->data_in_ready = true;
|
|
s->rregs[ESP_RSTAT] |= STAT_TC;
|
|
s->rregs[ESP_RINTR] |= INTR_BS;
|
|
esp_raise_irq(s);
|
|
|
|
/*
|
|
* If data is ready to transfer and the TI command has already
|
|
* been executed, start DMA immediately. Otherwise DMA will start
|
|
* when host sends the TI command
|
|
*/
|
|
if (s->ti_size && (s->rregs[ESP_CMD] == (CMD_TI | CMD_DMA))) {
|
|
esp_do_dma(s);
|
|
}
|
|
return;
|
|
}
|
|
|
|
if (s->ti_cmd == 0) {
|
|
/*
|
|
* Always perform the initial transfer upon reception of the next TI
|
|
* command to ensure the DMA/non-DMA status of the command is correct.
|
|
* It is not possible to use s->dma directly in the section below as
|
|
* some OSs send non-DMA NOP commands after a DMA transfer. Hence if the
|
|
* async data transfer is delayed then s->dma is set incorrectly.
|
|
*/
|
|
return;
|
|
}
|
|
|
|
if (s->ti_cmd & CMD_DMA) {
|
|
if (dmalen) {
|
|
esp_do_dma(s);
|
|
} else if (s->ti_size <= 0) {
|
|
/*
|
|
* If this was the last part of a DMA transfer then the
|
|
* completion interrupt is deferred to here.
|
|
*/
|
|
esp_dma_done(s);
|
|
esp_lower_drq(s);
|
|
}
|
|
} else {
|
|
esp_do_nodma(s);
|
|
}
|
|
}
|
|
|
|
static void handle_ti(ESPState *s)
|
|
{
|
|
uint32_t dmalen;
|
|
|
|
if (s->dma && !s->dma_enabled) {
|
|
s->dma_cb = handle_ti;
|
|
return;
|
|
}
|
|
|
|
s->ti_cmd = s->rregs[ESP_CMD];
|
|
if (s->dma) {
|
|
dmalen = esp_get_tc(s);
|
|
trace_esp_handle_ti(dmalen);
|
|
s->rregs[ESP_RSTAT] &= ~STAT_TC;
|
|
esp_do_dma(s);
|
|
} else {
|
|
trace_esp_handle_ti(s->ti_size);
|
|
esp_do_nodma(s);
|
|
}
|
|
}
|
|
|
|
void esp_hard_reset(ESPState *s)
|
|
{
|
|
memset(s->rregs, 0, ESP_REGS);
|
|
memset(s->wregs, 0, ESP_REGS);
|
|
s->tchi_written = 0;
|
|
s->ti_size = 0;
|
|
fifo8_reset(&s->fifo);
|
|
fifo8_reset(&s->cmdfifo);
|
|
s->dma = 0;
|
|
s->do_cmd = 0;
|
|
s->dma_cb = NULL;
|
|
|
|
s->rregs[ESP_CFG1] = 7;
|
|
}
|
|
|
|
static void esp_soft_reset(ESPState *s)
|
|
{
|
|
qemu_irq_lower(s->irq);
|
|
qemu_irq_lower(s->irq_data);
|
|
esp_hard_reset(s);
|
|
}
|
|
|
|
static void parent_esp_reset(ESPState *s, int irq, int level)
|
|
{
|
|
if (level) {
|
|
esp_soft_reset(s);
|
|
}
|
|
}
|
|
|
|
uint64_t esp_reg_read(ESPState *s, uint32_t saddr)
|
|
{
|
|
uint32_t val;
|
|
|
|
switch (saddr) {
|
|
case ESP_FIFO:
|
|
if (s->dma_memory_read && s->dma_memory_write &&
|
|
(s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) {
|
|
/* Data out. */
|
|
qemu_log_mask(LOG_UNIMP, "esp: PIO data read not implemented\n");
|
|
s->rregs[ESP_FIFO] = 0;
|
|
} else {
|
|
s->rregs[ESP_FIFO] = esp_fifo_pop(&s->fifo);
|
|
}
|
|
val = s->rregs[ESP_FIFO];
|
|
break;
|
|
case ESP_RINTR:
|
|
/*
|
|
* Clear sequence step, interrupt register and all status bits
|
|
* except TC
|
|
*/
|
|
val = s->rregs[ESP_RINTR];
|
|
s->rregs[ESP_RINTR] = 0;
|
|
s->rregs[ESP_RSTAT] &= ~STAT_TC;
|
|
s->rregs[ESP_RSEQ] = SEQ_0;
|
|
esp_lower_irq(s);
|
|
break;
|
|
case ESP_TCHI:
|
|
/* Return the unique id if the value has never been written */
|
|
if (!s->tchi_written) {
|
|
val = s->chip_id;
|
|
} else {
|
|
val = s->rregs[saddr];
|
|
}
|
|
break;
|
|
case ESP_RFLAGS:
|
|
/* Bottom 5 bits indicate number of bytes in FIFO */
|
|
val = fifo8_num_used(&s->fifo);
|
|
break;
|
|
default:
|
|
val = s->rregs[saddr];
|
|
break;
|
|
}
|
|
|
|
trace_esp_mem_readb(saddr, val);
|
|
return val;
|
|
}
|
|
|
|
void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)
|
|
{
|
|
trace_esp_mem_writeb(saddr, s->wregs[saddr], val);
|
|
switch (saddr) {
|
|
case ESP_TCHI:
|
|
s->tchi_written = true;
|
|
/* fall through */
|
|
case ESP_TCLO:
|
|
case ESP_TCMID:
|
|
s->rregs[ESP_RSTAT] &= ~STAT_TC;
|
|
break;
|
|
case ESP_FIFO:
|
|
if (s->do_cmd) {
|
|
esp_fifo_push(&s->cmdfifo, val);
|
|
} else {
|
|
esp_fifo_push(&s->fifo, val);
|
|
}
|
|
|
|
/* Non-DMA transfers raise an interrupt after every byte */
|
|
if (s->rregs[ESP_CMD] == CMD_TI) {
|
|
s->rregs[ESP_RINTR] |= INTR_FC | INTR_BS;
|
|
esp_raise_irq(s);
|
|
}
|
|
break;
|
|
case ESP_CMD:
|
|
s->rregs[saddr] = val;
|
|
if (val & CMD_DMA) {
|
|
s->dma = 1;
|
|
/* Reload DMA counter. */
|
|
if (esp_get_stc(s) == 0) {
|
|
esp_set_tc(s, 0x10000);
|
|
} else {
|
|
esp_set_tc(s, esp_get_stc(s));
|
|
}
|
|
} else {
|
|
s->dma = 0;
|
|
}
|
|
switch (val & CMD_CMD) {
|
|
case CMD_NOP:
|
|
trace_esp_mem_writeb_cmd_nop(val);
|
|
break;
|
|
case CMD_FLUSH:
|
|
trace_esp_mem_writeb_cmd_flush(val);
|
|
fifo8_reset(&s->fifo);
|
|
break;
|
|
case CMD_RESET:
|
|
trace_esp_mem_writeb_cmd_reset(val);
|
|
esp_soft_reset(s);
|
|
break;
|
|
case CMD_BUSRESET:
|
|
trace_esp_mem_writeb_cmd_bus_reset(val);
|
|
if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) {
|
|
s->rregs[ESP_RINTR] |= INTR_RST;
|
|
esp_raise_irq(s);
|
|
}
|
|
break;
|
|
case CMD_TI:
|
|
trace_esp_mem_writeb_cmd_ti(val);
|
|
handle_ti(s);
|
|
break;
|
|
case CMD_ICCS:
|
|
trace_esp_mem_writeb_cmd_iccs(val);
|
|
write_response(s);
|
|
s->rregs[ESP_RINTR] |= INTR_FC;
|
|
s->rregs[ESP_RSTAT] |= STAT_MI;
|
|
break;
|
|
case CMD_MSGACC:
|
|
trace_esp_mem_writeb_cmd_msgacc(val);
|
|
s->rregs[ESP_RINTR] |= INTR_DC;
|
|
s->rregs[ESP_RSEQ] = 0;
|
|
s->rregs[ESP_RFLAGS] = 0;
|
|
esp_raise_irq(s);
|
|
break;
|
|
case CMD_PAD:
|
|
trace_esp_mem_writeb_cmd_pad(val);
|
|
s->rregs[ESP_RSTAT] = STAT_TC;
|
|
s->rregs[ESP_RINTR] |= INTR_FC;
|
|
s->rregs[ESP_RSEQ] = 0;
|
|
break;
|
|
case CMD_SATN:
|
|
trace_esp_mem_writeb_cmd_satn(val);
|
|
break;
|
|
case CMD_RSTATN:
|
|
trace_esp_mem_writeb_cmd_rstatn(val);
|
|
break;
|
|
case CMD_SEL:
|
|
trace_esp_mem_writeb_cmd_sel(val);
|
|
handle_s_without_atn(s);
|
|
break;
|
|
case CMD_SELATN:
|
|
trace_esp_mem_writeb_cmd_selatn(val);
|
|
handle_satn(s);
|
|
break;
|
|
case CMD_SELATNS:
|
|
trace_esp_mem_writeb_cmd_selatns(val);
|
|
handle_satn_stop(s);
|
|
break;
|
|
case CMD_ENSEL:
|
|
trace_esp_mem_writeb_cmd_ensel(val);
|
|
s->rregs[ESP_RINTR] = 0;
|
|
break;
|
|
case CMD_DISSEL:
|
|
trace_esp_mem_writeb_cmd_dissel(val);
|
|
s->rregs[ESP_RINTR] = 0;
|
|
esp_raise_irq(s);
|
|
break;
|
|
default:
|
|
trace_esp_error_unhandled_command(val);
|
|
break;
|
|
}
|
|
break;
|
|
case ESP_WBUSID ... ESP_WSYNO:
|
|
break;
|
|
case ESP_CFG1:
|
|
case ESP_CFG2: case ESP_CFG3:
|
|
case ESP_RES3: case ESP_RES4:
|
|
s->rregs[saddr] = val;
|
|
break;
|
|
case ESP_WCCF ... ESP_WTEST:
|
|
break;
|
|
default:
|
|
trace_esp_error_invalid_write(val, saddr);
|
|
return;
|
|
}
|
|
s->wregs[saddr] = val;
|
|
}
|
|
|
|
static bool esp_mem_accepts(void *opaque, hwaddr addr,
|
|
unsigned size, bool is_write,
|
|
MemTxAttrs attrs)
|
|
{
|
|
return (size == 1) || (is_write && size == 4);
|
|
}
|
|
|
|
static bool esp_is_before_version_5(void *opaque, int version_id)
|
|
{
|
|
ESPState *s = ESP(opaque);
|
|
|
|
version_id = MIN(version_id, s->mig_version_id);
|
|
return version_id < 5;
|
|
}
|
|
|
|
static bool esp_is_version_5(void *opaque, int version_id)
|
|
{
|
|
ESPState *s = ESP(opaque);
|
|
|
|
version_id = MIN(version_id, s->mig_version_id);
|
|
return version_id == 5;
|
|
}
|
|
|
|
int esp_pre_save(void *opaque)
|
|
{
|
|
ESPState *s = ESP(object_resolve_path_component(
|
|
OBJECT(opaque), "esp"));
|
|
|
|
s->mig_version_id = vmstate_esp.version_id;
|
|
return 0;
|
|
}
|
|
|
|
static int esp_post_load(void *opaque, int version_id)
|
|
{
|
|
ESPState *s = ESP(opaque);
|
|
int len, i;
|
|
|
|
version_id = MIN(version_id, s->mig_version_id);
|
|
|
|
if (version_id < 5) {
|
|
esp_set_tc(s, s->mig_dma_left);
|
|
|
|
/* Migrate ti_buf to fifo */
|
|
len = s->mig_ti_wptr - s->mig_ti_rptr;
|
|
for (i = 0; i < len; i++) {
|
|
fifo8_push(&s->fifo, s->mig_ti_buf[i]);
|
|
}
|
|
|
|
/* Migrate cmdbuf to cmdfifo */
|
|
for (i = 0; i < s->mig_cmdlen; i++) {
|
|
fifo8_push(&s->cmdfifo, s->mig_cmdbuf[i]);
|
|
}
|
|
}
|
|
|
|
s->mig_version_id = vmstate_esp.version_id;
|
|
return 0;
|
|
}
|
|
|
|
const VMStateDescription vmstate_esp = {
|
|
.name = "esp",
|
|
.version_id = 5,
|
|
.minimum_version_id = 3,
|
|
.post_load = esp_post_load,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_BUFFER(rregs, ESPState),
|
|
VMSTATE_BUFFER(wregs, ESPState),
|
|
VMSTATE_INT32(ti_size, ESPState),
|
|
VMSTATE_UINT32_TEST(mig_ti_rptr, ESPState, esp_is_before_version_5),
|
|
VMSTATE_UINT32_TEST(mig_ti_wptr, ESPState, esp_is_before_version_5),
|
|
VMSTATE_BUFFER_TEST(mig_ti_buf, ESPState, esp_is_before_version_5),
|
|
VMSTATE_UINT32(status, ESPState),
|
|
VMSTATE_UINT32_TEST(mig_deferred_status, ESPState,
|
|
esp_is_before_version_5),
|
|
VMSTATE_BOOL_TEST(mig_deferred_complete, ESPState,
|
|
esp_is_before_version_5),
|
|
VMSTATE_UINT32(dma, ESPState),
|
|
VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 0,
|
|
esp_is_before_version_5, 0, 16),
|
|
VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 4,
|
|
esp_is_before_version_5, 16,
|
|
sizeof(typeof_field(ESPState, mig_cmdbuf))),
|
|
VMSTATE_UINT32_TEST(mig_cmdlen, ESPState, esp_is_before_version_5),
|
|
VMSTATE_UINT32(do_cmd, ESPState),
|
|
VMSTATE_UINT32_TEST(mig_dma_left, ESPState, esp_is_before_version_5),
|
|
VMSTATE_BOOL_TEST(data_in_ready, ESPState, esp_is_version_5),
|
|
VMSTATE_UINT8_TEST(cmdfifo_cdb_offset, ESPState, esp_is_version_5),
|
|
VMSTATE_FIFO8_TEST(fifo, ESPState, esp_is_version_5),
|
|
VMSTATE_FIFO8_TEST(cmdfifo, ESPState, esp_is_version_5),
|
|
VMSTATE_UINT8_TEST(ti_cmd, ESPState, esp_is_version_5),
|
|
VMSTATE_END_OF_LIST()
|
|
},
|
|
};
|
|
|
|
static void sysbus_esp_mem_write(void *opaque, hwaddr addr,
|
|
uint64_t val, unsigned int size)
|
|
{
|
|
SysBusESPState *sysbus = opaque;
|
|
ESPState *s = ESP(&sysbus->esp);
|
|
uint32_t saddr;
|
|
|
|
saddr = addr >> sysbus->it_shift;
|
|
esp_reg_write(s, saddr, val);
|
|
}
|
|
|
|
static uint64_t sysbus_esp_mem_read(void *opaque, hwaddr addr,
|
|
unsigned int size)
|
|
{
|
|
SysBusESPState *sysbus = opaque;
|
|
ESPState *s = ESP(&sysbus->esp);
|
|
uint32_t saddr;
|
|
|
|
saddr = addr >> sysbus->it_shift;
|
|
return esp_reg_read(s, saddr);
|
|
}
|
|
|
|
static const MemoryRegionOps sysbus_esp_mem_ops = {
|
|
.read = sysbus_esp_mem_read,
|
|
.write = sysbus_esp_mem_write,
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
.valid.accepts = esp_mem_accepts,
|
|
};
|
|
|
|
static void sysbus_esp_pdma_write(void *opaque, hwaddr addr,
|
|
uint64_t val, unsigned int size)
|
|
{
|
|
SysBusESPState *sysbus = opaque;
|
|
ESPState *s = ESP(&sysbus->esp);
|
|
uint32_t dmalen;
|
|
|
|
trace_esp_pdma_write(size);
|
|
|
|
switch (size) {
|
|
case 1:
|
|
esp_pdma_write(s, val);
|
|
break;
|
|
case 2:
|
|
esp_pdma_write(s, val >> 8);
|
|
esp_pdma_write(s, val);
|
|
break;
|
|
}
|
|
dmalen = esp_get_tc(s);
|
|
if (dmalen == 0 || fifo8_num_free(&s->fifo) < 2) {
|
|
s->pdma_cb(s);
|
|
}
|
|
}
|
|
|
|
static uint64_t sysbus_esp_pdma_read(void *opaque, hwaddr addr,
|
|
unsigned int size)
|
|
{
|
|
SysBusESPState *sysbus = opaque;
|
|
ESPState *s = ESP(&sysbus->esp);
|
|
uint64_t val = 0;
|
|
|
|
trace_esp_pdma_read(size);
|
|
|
|
switch (size) {
|
|
case 1:
|
|
val = esp_pdma_read(s);
|
|
break;
|
|
case 2:
|
|
val = esp_pdma_read(s);
|
|
val = (val << 8) | esp_pdma_read(s);
|
|
break;
|
|
}
|
|
if (fifo8_num_used(&s->fifo) < 2) {
|
|
s->pdma_cb(s);
|
|
}
|
|
return val;
|
|
}
|
|
|
|
static const MemoryRegionOps sysbus_esp_pdma_ops = {
|
|
.read = sysbus_esp_pdma_read,
|
|
.write = sysbus_esp_pdma_write,
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
.valid.min_access_size = 1,
|
|
.valid.max_access_size = 4,
|
|
.impl.min_access_size = 1,
|
|
.impl.max_access_size = 2,
|
|
};
|
|
|
|
static const struct SCSIBusInfo esp_scsi_info = {
|
|
.tcq = false,
|
|
.max_target = ESP_MAX_DEVS,
|
|
.max_lun = 7,
|
|
|
|
.transfer_data = esp_transfer_data,
|
|
.complete = esp_command_complete,
|
|
.cancel = esp_request_cancelled
|
|
};
|
|
|
|
static void sysbus_esp_gpio_demux(void *opaque, int irq, int level)
|
|
{
|
|
SysBusESPState *sysbus = SYSBUS_ESP(opaque);
|
|
ESPState *s = ESP(&sysbus->esp);
|
|
|
|
switch (irq) {
|
|
case 0:
|
|
parent_esp_reset(s, irq, level);
|
|
break;
|
|
case 1:
|
|
esp_dma_enable(opaque, irq, level);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void sysbus_esp_realize(DeviceState *dev, Error **errp)
|
|
{
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
|
|
SysBusESPState *sysbus = SYSBUS_ESP(dev);
|
|
ESPState *s = ESP(&sysbus->esp);
|
|
|
|
if (!qdev_realize(DEVICE(s), NULL, errp)) {
|
|
return;
|
|
}
|
|
|
|
sysbus_init_irq(sbd, &s->irq);
|
|
sysbus_init_irq(sbd, &s->irq_data);
|
|
assert(sysbus->it_shift != -1);
|
|
|
|
s->chip_id = TCHI_FAS100A;
|
|
memory_region_init_io(&sysbus->iomem, OBJECT(sysbus), &sysbus_esp_mem_ops,
|
|
sysbus, "esp-regs", ESP_REGS << sysbus->it_shift);
|
|
sysbus_init_mmio(sbd, &sysbus->iomem);
|
|
memory_region_init_io(&sysbus->pdma, OBJECT(sysbus), &sysbus_esp_pdma_ops,
|
|
sysbus, "esp-pdma", 4);
|
|
sysbus_init_mmio(sbd, &sysbus->pdma);
|
|
|
|
qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2);
|
|
|
|
scsi_bus_new(&s->bus, sizeof(s->bus), dev, &esp_scsi_info, NULL);
|
|
}
|
|
|
|
static void sysbus_esp_hard_reset(DeviceState *dev)
|
|
{
|
|
SysBusESPState *sysbus = SYSBUS_ESP(dev);
|
|
ESPState *s = ESP(&sysbus->esp);
|
|
|
|
esp_hard_reset(s);
|
|
}
|
|
|
|
static void sysbus_esp_init(Object *obj)
|
|
{
|
|
SysBusESPState *sysbus = SYSBUS_ESP(obj);
|
|
|
|
object_initialize_child(obj, "esp", &sysbus->esp, TYPE_ESP);
|
|
}
|
|
|
|
static const VMStateDescription vmstate_sysbus_esp_scsi = {
|
|
.name = "sysbusespscsi",
|
|
.version_id = 2,
|
|
.minimum_version_id = 1,
|
|
.pre_save = esp_pre_save,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT8_V(esp.mig_version_id, SysBusESPState, 2),
|
|
VMSTATE_STRUCT(esp, SysBusESPState, 0, vmstate_esp, ESPState),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static void sysbus_esp_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
dc->realize = sysbus_esp_realize;
|
|
dc->reset = sysbus_esp_hard_reset;
|
|
dc->vmsd = &vmstate_sysbus_esp_scsi;
|
|
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
|
|
}
|
|
|
|
static const TypeInfo sysbus_esp_info = {
|
|
.name = TYPE_SYSBUS_ESP,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_init = sysbus_esp_init,
|
|
.instance_size = sizeof(SysBusESPState),
|
|
.class_init = sysbus_esp_class_init,
|
|
};
|
|
|
|
static void esp_finalize(Object *obj)
|
|
{
|
|
ESPState *s = ESP(obj);
|
|
|
|
fifo8_destroy(&s->fifo);
|
|
fifo8_destroy(&s->cmdfifo);
|
|
}
|
|
|
|
static void esp_init(Object *obj)
|
|
{
|
|
ESPState *s = ESP(obj);
|
|
|
|
fifo8_create(&s->fifo, ESP_FIFO_SZ);
|
|
fifo8_create(&s->cmdfifo, ESP_CMDFIFO_SZ);
|
|
}
|
|
|
|
static void esp_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
/* internal device for sysbusesp/pciespscsi, not user-creatable */
|
|
dc->user_creatable = false;
|
|
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
|
|
}
|
|
|
|
static const TypeInfo esp_info = {
|
|
.name = TYPE_ESP,
|
|
.parent = TYPE_DEVICE,
|
|
.instance_init = esp_init,
|
|
.instance_finalize = esp_finalize,
|
|
.instance_size = sizeof(ESPState),
|
|
.class_init = esp_class_init,
|
|
};
|
|
|
|
static void esp_register_types(void)
|
|
{
|
|
type_register_static(&sysbus_esp_info);
|
|
type_register_static(&esp_info);
|
|
}
|
|
|
|
type_init(esp_register_types)
|