022b4ecf77
The unit-stride fault-only-fault load instructions are used to vectorize loops with data-dependent exit conditions(while loops). These instructions execute as a regular load except that they will only take a trap on element 0. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200701152549.1218-9-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
269 lines
12 KiB
Plaintext
269 lines
12 KiB
Plaintext
#
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# RISC-V translation routines for the RVXI Base Integer Instruction Set.
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#
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# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
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# Bastian Koppelmann, kbastian@mail.uni-paderborn.de
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms and conditions of the GNU General Public License,
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# version 2 or later, as published by the Free Software Foundation.
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#
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# This program is distributed in the hope it will be useful, but WITHOUT
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# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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# more details.
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#
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# You should have received a copy of the GNU General Public License along with
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# this program. If not, see <http://www.gnu.org/licenses/>.
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# Fields:
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%rs3 27:5
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%rs2 20:5
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%rs1 15:5
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%rd 7:5
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%sh10 20:10
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%csr 20:12
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%rm 12:3
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%nf 29:3 !function=ex_plus_1
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# immediates:
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%imm_i 20:s12
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%imm_s 25:s7 7:5
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%imm_b 31:s1 7:1 25:6 8:4 !function=ex_shift_1
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%imm_j 31:s1 12:8 20:1 21:10 !function=ex_shift_1
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%imm_u 12:s20 !function=ex_shift_12
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# Argument sets:
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&empty
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&b imm rs2 rs1
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&i imm rs1 rd
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&j imm rd
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&r rd rs1 rs2
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&s imm rs1 rs2
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&u imm rd
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&shift shamt rs1 rd
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&atomic aq rl rs2 rs1 rd
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&r2nfvm vm rd rs1 nf
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&rnfvm vm rd rs1 rs2 nf
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# Formats 32:
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@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd
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@i ............ ..... ... ..... ....... &i imm=%imm_i %rs1 %rd
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@b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1
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@s ....... ..... ..... ... ..... ....... &s imm=%imm_s %rs2 %rs1
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@u .................... ..... ....... &u imm=%imm_u %rd
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@j .................... ..... ....... &j imm=%imm_j %rd
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@sh ...... ...... ..... ... ..... ....... &shift shamt=%sh10 %rs1 %rd
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@csr ............ ..... ... ..... ....... %csr %rs1 %rd
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@atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd
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@atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2 %rs1 %rd
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@r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd
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@r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
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@r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd
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@r2 ....... ..... ..... ... ..... ....... %rs1 %rd
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@r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd
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@r_nfvm ... ... vm:1 ..... ..... ... ..... ....... &rnfvm %nf %rs2 %rs1 %rd
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@r2_zimm . zimm:11 ..... ... ..... ....... %rs1 %rd
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@hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1
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@hfence_vvma ....... ..... ..... ... ..... ....... %rs2 %rs1
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@sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1
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@sfence_vm ....... ..... ..... ... ..... ....... %rs1
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# *** Privileged Instructions ***
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ecall 000000000000 00000 000 00000 1110011
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ebreak 000000000001 00000 000 00000 1110011
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uret 0000000 00010 00000 000 00000 1110011
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sret 0001000 00010 00000 000 00000 1110011
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mret 0011000 00010 00000 000 00000 1110011
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wfi 0001000 00101 00000 000 00000 1110011
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sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma
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sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm
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# *** RV32I Base Instruction Set ***
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lui .................... ..... 0110111 @u
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auipc .................... ..... 0010111 @u
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jal .................... ..... 1101111 @j
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jalr ............ ..... 000 ..... 1100111 @i
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beq ....... ..... ..... 000 ..... 1100011 @b
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bne ....... ..... ..... 001 ..... 1100011 @b
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blt ....... ..... ..... 100 ..... 1100011 @b
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bge ....... ..... ..... 101 ..... 1100011 @b
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bltu ....... ..... ..... 110 ..... 1100011 @b
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bgeu ....... ..... ..... 111 ..... 1100011 @b
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lb ............ ..... 000 ..... 0000011 @i
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lh ............ ..... 001 ..... 0000011 @i
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lw ............ ..... 010 ..... 0000011 @i
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lbu ............ ..... 100 ..... 0000011 @i
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lhu ............ ..... 101 ..... 0000011 @i
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sb ....... ..... ..... 000 ..... 0100011 @s
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sh ....... ..... ..... 001 ..... 0100011 @s
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sw ....... ..... ..... 010 ..... 0100011 @s
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addi ............ ..... 000 ..... 0010011 @i
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slti ............ ..... 010 ..... 0010011 @i
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sltiu ............ ..... 011 ..... 0010011 @i
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xori ............ ..... 100 ..... 0010011 @i
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ori ............ ..... 110 ..... 0010011 @i
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andi ............ ..... 111 ..... 0010011 @i
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slli 00.... ...... ..... 001 ..... 0010011 @sh
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srli 00.... ...... ..... 101 ..... 0010011 @sh
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srai 01.... ...... ..... 101 ..... 0010011 @sh
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add 0000000 ..... ..... 000 ..... 0110011 @r
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sub 0100000 ..... ..... 000 ..... 0110011 @r
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sll 0000000 ..... ..... 001 ..... 0110011 @r
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slt 0000000 ..... ..... 010 ..... 0110011 @r
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sltu 0000000 ..... ..... 011 ..... 0110011 @r
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xor 0000000 ..... ..... 100 ..... 0110011 @r
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srl 0000000 ..... ..... 101 ..... 0110011 @r
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sra 0100000 ..... ..... 101 ..... 0110011 @r
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or 0000000 ..... ..... 110 ..... 0110011 @r
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and 0000000 ..... ..... 111 ..... 0110011 @r
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fence ---- pred:4 succ:4 ----- 000 ----- 0001111
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fence_i ---- ---- ---- ----- 001 ----- 0001111
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csrrw ............ ..... 001 ..... 1110011 @csr
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csrrs ............ ..... 010 ..... 1110011 @csr
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csrrc ............ ..... 011 ..... 1110011 @csr
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csrrwi ............ ..... 101 ..... 1110011 @csr
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csrrsi ............ ..... 110 ..... 1110011 @csr
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csrrci ............ ..... 111 ..... 1110011 @csr
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# *** RV32M Standard Extension ***
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mul 0000001 ..... ..... 000 ..... 0110011 @r
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mulh 0000001 ..... ..... 001 ..... 0110011 @r
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mulhsu 0000001 ..... ..... 010 ..... 0110011 @r
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mulhu 0000001 ..... ..... 011 ..... 0110011 @r
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div 0000001 ..... ..... 100 ..... 0110011 @r
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divu 0000001 ..... ..... 101 ..... 0110011 @r
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rem 0000001 ..... ..... 110 ..... 0110011 @r
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remu 0000001 ..... ..... 111 ..... 0110011 @r
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# *** RV32A Standard Extension ***
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lr_w 00010 . . 00000 ..... 010 ..... 0101111 @atom_ld
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sc_w 00011 . . ..... ..... 010 ..... 0101111 @atom_st
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amoswap_w 00001 . . ..... ..... 010 ..... 0101111 @atom_st
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amoadd_w 00000 . . ..... ..... 010 ..... 0101111 @atom_st
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amoxor_w 00100 . . ..... ..... 010 ..... 0101111 @atom_st
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amoand_w 01100 . . ..... ..... 010 ..... 0101111 @atom_st
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amoor_w 01000 . . ..... ..... 010 ..... 0101111 @atom_st
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amomin_w 10000 . . ..... ..... 010 ..... 0101111 @atom_st
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amomax_w 10100 . . ..... ..... 010 ..... 0101111 @atom_st
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amominu_w 11000 . . ..... ..... 010 ..... 0101111 @atom_st
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amomaxu_w 11100 . . ..... ..... 010 ..... 0101111 @atom_st
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# *** RV32F Standard Extension ***
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flw ............ ..... 010 ..... 0000111 @i
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fsw ....... ..... ..... 010 ..... 0100111 @s
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fmadd_s ..... 00 ..... ..... ... ..... 1000011 @r4_rm
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fmsub_s ..... 00 ..... ..... ... ..... 1000111 @r4_rm
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fnmsub_s ..... 00 ..... ..... ... ..... 1001011 @r4_rm
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fnmadd_s ..... 00 ..... ..... ... ..... 1001111 @r4_rm
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fadd_s 0000000 ..... ..... ... ..... 1010011 @r_rm
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fsub_s 0000100 ..... ..... ... ..... 1010011 @r_rm
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fmul_s 0001000 ..... ..... ... ..... 1010011 @r_rm
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fdiv_s 0001100 ..... ..... ... ..... 1010011 @r_rm
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fsqrt_s 0101100 00000 ..... ... ..... 1010011 @r2_rm
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fsgnj_s 0010000 ..... ..... 000 ..... 1010011 @r
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fsgnjn_s 0010000 ..... ..... 001 ..... 1010011 @r
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fsgnjx_s 0010000 ..... ..... 010 ..... 1010011 @r
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fmin_s 0010100 ..... ..... 000 ..... 1010011 @r
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fmax_s 0010100 ..... ..... 001 ..... 1010011 @r
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fcvt_w_s 1100000 00000 ..... ... ..... 1010011 @r2_rm
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fcvt_wu_s 1100000 00001 ..... ... ..... 1010011 @r2_rm
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fmv_x_w 1110000 00000 ..... 000 ..... 1010011 @r2
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feq_s 1010000 ..... ..... 010 ..... 1010011 @r
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flt_s 1010000 ..... ..... 001 ..... 1010011 @r
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fle_s 1010000 ..... ..... 000 ..... 1010011 @r
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fclass_s 1110000 00000 ..... 001 ..... 1010011 @r2
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fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_rm
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fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm
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fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2
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# *** RV32D Standard Extension ***
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fld ............ ..... 011 ..... 0000111 @i
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fsd ....... ..... ..... 011 ..... 0100111 @s
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fmadd_d ..... 01 ..... ..... ... ..... 1000011 @r4_rm
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fmsub_d ..... 01 ..... ..... ... ..... 1000111 @r4_rm
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fnmsub_d ..... 01 ..... ..... ... ..... 1001011 @r4_rm
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fnmadd_d ..... 01 ..... ..... ... ..... 1001111 @r4_rm
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fadd_d 0000001 ..... ..... ... ..... 1010011 @r_rm
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fsub_d 0000101 ..... ..... ... ..... 1010011 @r_rm
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fmul_d 0001001 ..... ..... ... ..... 1010011 @r_rm
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fdiv_d 0001101 ..... ..... ... ..... 1010011 @r_rm
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fsqrt_d 0101101 00000 ..... ... ..... 1010011 @r2_rm
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fsgnj_d 0010001 ..... ..... 000 ..... 1010011 @r
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fsgnjn_d 0010001 ..... ..... 001 ..... 1010011 @r
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fsgnjx_d 0010001 ..... ..... 010 ..... 1010011 @r
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fmin_d 0010101 ..... ..... 000 ..... 1010011 @r
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fmax_d 0010101 ..... ..... 001 ..... 1010011 @r
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fcvt_s_d 0100000 00001 ..... ... ..... 1010011 @r2_rm
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fcvt_d_s 0100001 00000 ..... ... ..... 1010011 @r2_rm
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feq_d 1010001 ..... ..... 010 ..... 1010011 @r
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flt_d 1010001 ..... ..... 001 ..... 1010011 @r
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fle_d 1010001 ..... ..... 000 ..... 1010011 @r
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fclass_d 1110001 00000 ..... 001 ..... 1010011 @r2
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fcvt_w_d 1100001 00000 ..... ... ..... 1010011 @r2_rm
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fcvt_wu_d 1100001 00001 ..... ... ..... 1010011 @r2_rm
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fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm
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fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm
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# *** RV32H Base Instruction Set ***
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hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma
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hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma
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# *** RV32V Extension ***
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# *** Vector loads and stores are encoded within LOADFP/STORE-FP ***
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vlb_v ... 100 . 00000 ..... 000 ..... 0000111 @r2_nfvm
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vlh_v ... 100 . 00000 ..... 101 ..... 0000111 @r2_nfvm
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vlw_v ... 100 . 00000 ..... 110 ..... 0000111 @r2_nfvm
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vle_v ... 000 . 00000 ..... 111 ..... 0000111 @r2_nfvm
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vlbu_v ... 000 . 00000 ..... 000 ..... 0000111 @r2_nfvm
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vlhu_v ... 000 . 00000 ..... 101 ..... 0000111 @r2_nfvm
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vlwu_v ... 000 . 00000 ..... 110 ..... 0000111 @r2_nfvm
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vlbff_v ... 100 . 10000 ..... 000 ..... 0000111 @r2_nfvm
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vlhff_v ... 100 . 10000 ..... 101 ..... 0000111 @r2_nfvm
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vlwff_v ... 100 . 10000 ..... 110 ..... 0000111 @r2_nfvm
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vleff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm
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vlbuff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm
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vlhuff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm
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vlwuff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm
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vsb_v ... 000 . 00000 ..... 000 ..... 0100111 @r2_nfvm
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vsh_v ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm
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vsw_v ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm
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vse_v ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm
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vlsb_v ... 110 . ..... ..... 000 ..... 0000111 @r_nfvm
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vlsh_v ... 110 . ..... ..... 101 ..... 0000111 @r_nfvm
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vlsw_v ... 110 . ..... ..... 110 ..... 0000111 @r_nfvm
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vlse_v ... 010 . ..... ..... 111 ..... 0000111 @r_nfvm
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vlsbu_v ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm
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vlshu_v ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm
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vlswu_v ... 010 . ..... ..... 110 ..... 0000111 @r_nfvm
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vssb_v ... 010 . ..... ..... 000 ..... 0100111 @r_nfvm
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vssh_v ... 010 . ..... ..... 101 ..... 0100111 @r_nfvm
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vssw_v ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm
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vsse_v ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm
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vlxb_v ... 111 . ..... ..... 000 ..... 0000111 @r_nfvm
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vlxh_v ... 111 . ..... ..... 101 ..... 0000111 @r_nfvm
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vlxw_v ... 111 . ..... ..... 110 ..... 0000111 @r_nfvm
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vlxe_v ... 011 . ..... ..... 111 ..... 0000111 @r_nfvm
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vlxbu_v ... 011 . ..... ..... 000 ..... 0000111 @r_nfvm
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vlxhu_v ... 011 . ..... ..... 101 ..... 0000111 @r_nfvm
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vlxwu_v ... 011 . ..... ..... 110 ..... 0000111 @r_nfvm
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# Vector ordered-indexed and unordered-indexed store insns.
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vsxb_v ... -11 . ..... ..... 000 ..... 0100111 @r_nfvm
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vsxh_v ... -11 . ..... ..... 101 ..... 0100111 @r_nfvm
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vsxw_v ... -11 . ..... ..... 110 ..... 0100111 @r_nfvm
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vsxe_v ... -11 . ..... ..... 111 ..... 0100111 @r_nfvm
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# *** new major opcode OP-V ***
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vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
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vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
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