669b498301
Re-implemented the interconnect between the Xilinx AXI ethernet and DMA controllers. A QOM interface "stream" is created, for the two stream interfaces. As per Edgars request, this is designed to be more generic than AXI-stream, so in the future we may see more clients of this interface beyond AXI stream. This is based primarily on Paolos original refactoring of the interconnect. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
24 lines
495 B
C
24 lines
495 B
C
#include "stream.h"
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void
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stream_push(StreamSlave *sink, uint8_t *buf, size_t len, uint32_t *app)
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{
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StreamSlaveClass *k = STREAM_SLAVE_GET_CLASS(sink);
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k->push(sink, buf, len, app);
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}
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static TypeInfo stream_slave_info = {
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.name = TYPE_STREAM_SLAVE,
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.parent = TYPE_INTERFACE,
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.class_size = sizeof(StreamSlaveClass),
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};
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static void stream_slave_register_types(void)
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{
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type_register_static(&stream_slave_info);
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}
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type_init(stream_slave_register_types)
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