430 lines
14 KiB
C
430 lines
14 KiB
C
/*
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* Raspberry Pi emulation (c) 2012 Gregory Estrade
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* Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous
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*
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* Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft
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* Written by Andrew Baumann
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu/module.h"
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#include "hw/arm/bcm2836.h"
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#include "hw/arm/raspi_platform.h"
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#include "hw/arm/raspi4_platform.h"
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#include "hw/sysbus.h"
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#include "trace.h"
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typedef struct BCM283XClass {
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/*< private >*/
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DeviceClass parent_class;
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/*< public >*/
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const char *name;
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const char *cpu_type;
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unsigned core_count;
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hwaddr peri_base; /* Peripheral base address seen by the CPU */
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hwaddr ctrl_base; /* Interrupt controller and mailboxes etc. */
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hwaddr gic_base;
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int clusterid;
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} BCM283XClass;
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#define BCM283X_CLASS(klass) \
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OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X)
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#define BCM283X_GET_CLASS(obj) \
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OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X)
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static Property bcm2836_enabled_cores_property =
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DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus, 0);
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static void bcm2836_init(Object *obj)
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{
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BCM283XState *s = BCM283X(obj);
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BCM283XClass *bc = BCM283X_GET_CLASS(obj);
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int n;
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for (n = 0; n < bc->core_count; n++) {
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object_initialize_child(obj, "cpu[*]", &s->cpu[n].core,
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bc->cpu_type);
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}
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if (bc->core_count > 1) {
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qdev_property_add_static(DEVICE(obj), &bcm2836_enabled_cores_property);
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qdev_prop_set_uint32(DEVICE(obj), "enabled-cpus", bc->core_count);
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}
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if (bc->gic_base) {
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object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC);
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}
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if (bc->ctrl_base) {
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object_initialize_child(obj, "control", &s->control,
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TYPE_BCM2836_CONTROL);
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}
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object_initialize_child(obj, "peripherals", &s->peripherals,
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TYPE_BCM2835_PERIPHERALS);
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object_property_add_alias(obj, "board-rev", OBJECT(&s->peripherals),
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"board-rev");
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object_property_add_alias(obj, "vcram-size", OBJECT(&s->peripherals),
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"vcram-size");
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}
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static bool bcm283x_common_realize(DeviceState *dev, Error **errp)
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{
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BCM283XState *s = BCM283X(dev);
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BCM283XClass *bc = BCM283X_GET_CLASS(dev);
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Object *obj;
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/* common peripherals from bcm2835 */
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obj = object_property_get_link(OBJECT(dev), "ram", &error_abort);
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object_property_add_const_link(OBJECT(&s->peripherals), "ram", obj);
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->peripherals), errp)) {
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return false;
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}
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object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->peripherals),
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"sd-bus");
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sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->peripherals), 0,
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bc->peri_base, 1);
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return true;
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}
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static void bcm2835_realize(DeviceState *dev, Error **errp)
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{
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BCM283XState *s = BCM283X(dev);
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if (!bcm283x_common_realize(dev, errp)) {
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return;
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}
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if (!qdev_realize(DEVICE(&s->cpu[0].core), NULL, errp)) {
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return;
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}
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/* Connect irq/fiq outputs from the interrupt controller. */
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0,
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qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_IRQ));
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
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qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_FIQ));
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}
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static void bcm2836_realize(DeviceState *dev, Error **errp)
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{
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BCM283XState *s = BCM283X(dev);
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BCM283XClass *bc = BCM283X_GET_CLASS(dev);
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int n;
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if (!bcm283x_common_realize(dev, errp)) {
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return;
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}
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/* bcm2836 interrupt controller (and mailboxes, etc.) */
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->control), errp)) {
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->control), 0, bc->ctrl_base);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0,
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qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-irq", 0));
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
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qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));
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for (n = 0; n < BCM283X_NCPUS; n++) {
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/* TODO: this should be converted to a property of ARM_CPU */
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s->cpu[n].core.mp_affinity = (bc->clusterid << 8) | n;
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/* set periphbase/CBAR value for CPU-local registers */
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if (!object_property_set_int(OBJECT(&s->cpu[n].core), "reset-cbar",
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bc->peri_base, errp)) {
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return;
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}
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/* start powered off if not enabled */
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if (!object_property_set_bool(OBJECT(&s->cpu[n].core),
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"start-powered-off",
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n >= s->enabled_cpus,
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errp)) {
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return;
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}
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if (!qdev_realize(DEVICE(&s->cpu[n].core), NULL, errp)) {
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return;
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}
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/* Connect irq/fiq outputs from the interrupt controller. */
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qdev_connect_gpio_out_named(DEVICE(&s->control), "irq", n,
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qdev_get_gpio_in(DEVICE(&s->cpu[n].core), ARM_CPU_IRQ));
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qdev_connect_gpio_out_named(DEVICE(&s->control), "fiq", n,
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qdev_get_gpio_in(DEVICE(&s->cpu[n].core), ARM_CPU_FIQ));
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/* Connect timers from the CPU to the interrupt controller */
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qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_PHYS,
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qdev_get_gpio_in_named(DEVICE(&s->control), "cntpnsirq", n));
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qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_VIRT,
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qdev_get_gpio_in_named(DEVICE(&s->control), "cntvirq", n));
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qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_HYP,
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qdev_get_gpio_in_named(DEVICE(&s->control), "cnthpirq", n));
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qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_SEC,
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qdev_get_gpio_in_named(DEVICE(&s->control), "cntpsirq", n));
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}
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}
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static void bcm283x_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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/* Reason: Must be wired up in code (see raspi_init() function) */
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dc->user_creatable = false;
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}
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static void bcm2835_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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BCM283XClass *bc = BCM283X_CLASS(oc);
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bc->cpu_type = ARM_CPU_TYPE_NAME("arm1176");
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bc->core_count = 1;
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bc->peri_base = 0x20000000;
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dc->realize = bcm2835_realize;
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};
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static void bcm2836_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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BCM283XClass *bc = BCM283X_CLASS(oc);
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bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
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bc->core_count = BCM283X_NCPUS;
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bc->peri_base = 0x3f000000;
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bc->ctrl_base = 0x40000000;
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bc->clusterid = 0xf;
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dc->realize = bcm2836_realize;
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};
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#ifdef TARGET_AARCH64
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#define GIC400_MAINTAINANCE_IRQ 9
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#define GIC400_TIMER_NS_EL2_IRQ 10
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#define GIC400_TIMER_VIRT_IRQ 11
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#define GIC400_LEGACY_FIQ 12
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#define GIC400_TIMER_S_EL1_IRQ 13
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#define GIC400_TIMER_NS_EL1_IRQ 14
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#define GIC400_LEGACY_IRQ 15
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/* Number of external interrupt lines to configure the GIC with */
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#define GIC_NUM_IRQS 128
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#define PPI(cpu, irq) (GIC_NUM_IRQS + (cpu) * GIC_INTERNAL + GIC_NR_SGIS + irq)
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#define GIC_BASE_OFS 0x0000
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#define GIC_DIST_OFS 0x1000
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#define GIC_CPU_OFS 0x2000
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#define GIC_VIFACE_THIS_OFS 0x4000
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#define GIC_VIFACE_OTHER_OFS(cpu) (0x5000 + (cpu) * 0x200)
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#define GIC_VCPU_OFS 0x6000
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#define VIRTUAL_PMU_IRQ 7
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static void bcm2838_gic_set_irq(void *opaque, int irq, int level)
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{
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BCM283XState *s = (BCM283XState *)opaque;
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trace_bcm2838_gic_set_irq(irq, level);
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qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level);
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}
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static void bcm2838_realize(DeviceState *dev, Error **errp)
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{
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BCM283XState *s = BCM283X(dev);
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BCM283XClass *bc = BCM283X_GET_CLASS(dev);
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int n;
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if (!bcm283x_common_realize(dev, errp)) {
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return;
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}
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sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->peripherals), 0,
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bc->peri_base, 1);
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/* bcm2836 interrupt controller (and mailboxes, etc.) */
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->control), errp)) {
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->control), 0, bc->ctrl_base);
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/* Create cores */
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for (n = 0; n < bc->core_count; n++) {
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/* TODO: this should be converted to a property of ARM_CPU */
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s->cpu[n].core.mp_affinity = (bc->clusterid << 8) | n;
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/* set periphbase/CBAR value for CPU-local registers */
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if (!object_property_set_int(OBJECT(&s->cpu[n].core), "reset-cbar",
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bc->peri_base, errp)) {
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return;
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}
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/* start powered off if not enabled */
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if (!object_property_set_bool(OBJECT(&s->cpu[n].core),
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"start-powered-off",
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n >= s->enabled_cpus,
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errp)) {
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return;
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}
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if (!qdev_realize(DEVICE(&s->cpu[n].core), NULL, errp)) {
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return;
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}
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}
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if (!object_property_set_uint(OBJECT(&s->gic), "revision", 2, errp)) {
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return;
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}
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if (!object_property_set_uint(OBJECT(&s->gic), "num-cpu", BCM283X_NCPUS,
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errp)) {
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return;
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}
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if (!object_property_set_uint(OBJECT(&s->gic),
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"num-irq", GIC_NUM_IRQS + GIC_INTERNAL,
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errp)) {
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return;
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}
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if (!object_property_set_bool(OBJECT(&s->gic),
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"has-virtualization-extensions",
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true, errp)) {
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return;
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}
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) {
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0,
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bc->ctrl_base + bc->gic_base + GIC_DIST_OFS);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1,
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bc->ctrl_base + bc->gic_base + GIC_CPU_OFS);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2,
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bc->ctrl_base + bc->gic_base + GIC_VIFACE_THIS_OFS);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3,
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bc->ctrl_base + bc->gic_base + GIC_VCPU_OFS);
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for (n = 0; n < BCM283X_NCPUS; n++) {
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 4 + n,
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bc->ctrl_base + bc->gic_base + GIC_VIFACE_OTHER_OFS(n));
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}
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for (n = 0; n < BCM283X_NCPUS; n++) {
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DeviceState *cpudev = DEVICE(&s->cpu[n]);
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DeviceState *gicdev = DEVICE(&s->gic);
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/* Connect the GICv2 outputs to the CPU */
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), n,
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qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), n + BCM283X_NCPUS,
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qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), n + 2 * BCM283X_NCPUS,
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qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), n + 3 * BCM283X_NCPUS,
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qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), n + 4 * BCM283X_NCPUS,
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qdev_get_gpio_in(gicdev,
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PPI(n, GIC400_MAINTAINANCE_IRQ)));
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/* Connect UART0 to the interrupt controller */
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals.uart0), 0,
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qdev_get_gpio_in(gicdev, RPI4_INTERRUPT_UART0));
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/* Connect timers from the CPU to the interrupt controller */
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qdev_connect_gpio_out(cpudev, GTIMER_PHYS,
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qdev_get_gpio_in(gicdev, PPI(n, GIC400_TIMER_NS_EL1_IRQ)));
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qdev_connect_gpio_out(cpudev, GTIMER_VIRT,
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qdev_get_gpio_in(gicdev, PPI(n, GIC400_TIMER_VIRT_IRQ)));
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qdev_connect_gpio_out(cpudev, GTIMER_HYP,
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qdev_get_gpio_in(gicdev, PPI(n, GIC400_TIMER_NS_EL2_IRQ)));
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qdev_connect_gpio_out(cpudev, GTIMER_SEC,
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qdev_get_gpio_in(gicdev, PPI(n, GIC400_TIMER_S_EL1_IRQ)));
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/* PMU interrupt */
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qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
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qdev_get_gpio_in(gicdev, PPI(n, VIRTUAL_PMU_IRQ)));
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}
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/* Pass through inbound GPIO lines to the GIC */
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qdev_init_gpio_in(dev, bcm2838_gic_set_irq, GIC_NUM_IRQS);
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/* Pass through outbound IRQ lines from the GIC */
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qdev_pass_gpios(DEVICE(&s->gic), DEVICE(&s->peripherals), NULL);
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}
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static void bcm2837_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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BCM283XClass *bc = BCM283X_CLASS(oc);
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bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a53");
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bc->core_count = BCM283X_NCPUS;
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bc->peri_base = 0x3f000000;
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bc->ctrl_base = 0x40000000;
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bc->clusterid = 0x0;
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dc->realize = bcm2836_realize;
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};
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static void bcm2838_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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BCM283XClass *bc = BCM283X_CLASS(oc);
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bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a72");
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bc->core_count = BCM283X_NCPUS;
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bc->peri_base = 0xfe000000;
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bc->ctrl_base = 0xff800000;
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bc->gic_base = 0x40000;
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bc->clusterid = 0x0;
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dc->realize = bcm2838_realize;
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};
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#endif
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static const TypeInfo bcm283x_types[] = {
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{
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.name = TYPE_BCM2835,
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.parent = TYPE_BCM283X,
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.class_init = bcm2835_class_init,
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}, {
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.name = TYPE_BCM2836,
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.parent = TYPE_BCM283X,
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.class_init = bcm2836_class_init,
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#ifdef TARGET_AARCH64
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}, {
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.name = TYPE_BCM2837,
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.parent = TYPE_BCM283X,
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.class_init = bcm2837_class_init,
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}, {
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.name = TYPE_BCM2838,
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.parent = TYPE_BCM283X,
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.class_init = bcm2838_class_init,
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#endif
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}, {
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.name = TYPE_BCM283X,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(BCM283XState),
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.instance_init = bcm2836_init,
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.class_size = sizeof(BCM283XClass),
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.class_init = bcm283x_class_init,
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.abstract = true,
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}
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};
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DEFINE_TYPES(bcm283x_types)
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