Currently the XICS interrupt controller emulation uses a custom enum to specify whether a given interrupt is level-sensitive or message-triggered. This enum makes life awkward for saving the state, and isn't particularly useful since there are only two possibilities. This patch replaces the enum with a simple bool. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
772 lines
25 KiB
C
772 lines
25 KiB
C
/*
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* QEMU sPAPR PCI host originated from Uninorth PCI host
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*
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* Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation.
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* Copyright (C) 2011 David Gibson, IBM Corporation.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "pci.h"
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#include "msi.h"
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#include "msix.h"
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#include "pci_host.h"
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#include "hw/spapr.h"
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#include "hw/spapr_pci.h"
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#include "exec-memory.h"
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#include <libfdt.h>
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#include "trace.h"
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#include "hw/pci_internals.h"
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/* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */
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#define RTAS_QUERY_FN 0
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#define RTAS_CHANGE_FN 1
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#define RTAS_RESET_FN 2
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#define RTAS_CHANGE_MSI_FN 3
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#define RTAS_CHANGE_MSIX_FN 4
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/* Interrupt types to return on RTAS_CHANGE_* */
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#define RTAS_TYPE_MSI 1
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#define RTAS_TYPE_MSIX 2
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static sPAPRPHBState *find_phb(sPAPREnvironment *spapr, uint64_t buid)
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{
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sPAPRPHBState *sphb;
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QLIST_FOREACH(sphb, &spapr->phbs, list) {
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if (sphb->buid != buid) {
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continue;
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}
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return sphb;
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}
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return NULL;
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}
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static PCIDevice *find_dev(sPAPREnvironment *spapr, uint64_t buid,
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uint32_t config_addr)
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{
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sPAPRPHBState *sphb = find_phb(spapr, buid);
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PCIHostState *phb = PCI_HOST_BRIDGE(sphb);
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BusState *bus = BUS(phb->bus);
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BusChild *kid;
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int devfn = (config_addr >> 8) & 0xFF;
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if (!phb) {
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return NULL;
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}
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QTAILQ_FOREACH(kid, &bus->children, sibling) {
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PCIDevice *dev = (PCIDevice *)kid->child;
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if (dev->devfn == devfn) {
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return dev;
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}
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}
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return NULL;
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}
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static uint32_t rtas_pci_cfgaddr(uint32_t arg)
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{
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/* This handles the encoding of extended config space addresses */
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return ((arg >> 20) & 0xf00) | (arg & 0xff);
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}
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static void finish_read_pci_config(sPAPREnvironment *spapr, uint64_t buid,
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uint32_t addr, uint32_t size,
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target_ulong rets)
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{
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PCIDevice *pci_dev;
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uint32_t val;
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if ((size != 1) && (size != 2) && (size != 4)) {
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/* access must be 1, 2 or 4 bytes */
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rtas_st(rets, 0, -1);
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return;
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}
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pci_dev = find_dev(spapr, buid, addr);
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addr = rtas_pci_cfgaddr(addr);
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if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) {
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/* Access must be to a valid device, within bounds and
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* naturally aligned */
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rtas_st(rets, 0, -1);
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return;
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}
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val = pci_host_config_read_common(pci_dev, addr,
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pci_config_size(pci_dev), size);
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rtas_st(rets, 0, 0);
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rtas_st(rets, 1, val);
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}
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static void rtas_ibm_read_pci_config(sPAPREnvironment *spapr,
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uint32_t token, uint32_t nargs,
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target_ulong args,
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uint32_t nret, target_ulong rets)
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{
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uint64_t buid;
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uint32_t size, addr;
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if ((nargs != 4) || (nret != 2)) {
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rtas_st(rets, 0, -1);
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return;
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}
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buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
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size = rtas_ld(args, 3);
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addr = rtas_ld(args, 0);
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finish_read_pci_config(spapr, buid, addr, size, rets);
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}
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static void rtas_read_pci_config(sPAPREnvironment *spapr,
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uint32_t token, uint32_t nargs,
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target_ulong args,
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uint32_t nret, target_ulong rets)
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{
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uint32_t size, addr;
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if ((nargs != 2) || (nret != 2)) {
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rtas_st(rets, 0, -1);
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return;
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}
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size = rtas_ld(args, 1);
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addr = rtas_ld(args, 0);
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finish_read_pci_config(spapr, 0, addr, size, rets);
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}
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static void finish_write_pci_config(sPAPREnvironment *spapr, uint64_t buid,
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uint32_t addr, uint32_t size,
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uint32_t val, target_ulong rets)
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{
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PCIDevice *pci_dev;
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if ((size != 1) && (size != 2) && (size != 4)) {
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/* access must be 1, 2 or 4 bytes */
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rtas_st(rets, 0, -1);
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return;
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}
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pci_dev = find_dev(spapr, buid, addr);
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addr = rtas_pci_cfgaddr(addr);
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if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) {
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/* Access must be to a valid device, within bounds and
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* naturally aligned */
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rtas_st(rets, 0, -1);
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return;
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}
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pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev),
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val, size);
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rtas_st(rets, 0, 0);
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}
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static void rtas_ibm_write_pci_config(sPAPREnvironment *spapr,
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uint32_t token, uint32_t nargs,
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target_ulong args,
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uint32_t nret, target_ulong rets)
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{
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uint64_t buid;
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uint32_t val, size, addr;
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if ((nargs != 5) || (nret != 1)) {
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rtas_st(rets, 0, -1);
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return;
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}
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buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
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val = rtas_ld(args, 4);
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size = rtas_ld(args, 3);
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addr = rtas_ld(args, 0);
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finish_write_pci_config(spapr, buid, addr, size, val, rets);
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}
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static void rtas_write_pci_config(sPAPREnvironment *spapr,
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uint32_t token, uint32_t nargs,
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target_ulong args,
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uint32_t nret, target_ulong rets)
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{
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uint32_t val, size, addr;
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if ((nargs != 3) || (nret != 1)) {
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rtas_st(rets, 0, -1);
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return;
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}
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val = rtas_ld(args, 2);
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size = rtas_ld(args, 1);
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addr = rtas_ld(args, 0);
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finish_write_pci_config(spapr, 0, addr, size, val, rets);
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}
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/*
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* Find an entry with config_addr or returns the empty one if not found AND
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* alloc_new is set.
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* At the moment the msi_table entries are never released so there is
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* no point to look till the end of the list if we need to find the free entry.
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*/
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static int spapr_msicfg_find(sPAPRPHBState *phb, uint32_t config_addr,
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bool alloc_new)
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{
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int i;
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for (i = 0; i < SPAPR_MSIX_MAX_DEVS; ++i) {
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if (!phb->msi_table[i].nvec) {
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break;
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}
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if (phb->msi_table[i].config_addr == config_addr) {
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return i;
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}
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}
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if ((i < SPAPR_MSIX_MAX_DEVS) && alloc_new) {
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trace_spapr_pci_msi("Allocating new MSI config", i, config_addr);
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return i;
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}
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return -1;
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}
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/*
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* Set MSI/MSIX message data.
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* This is required for msi_notify()/msix_notify() which
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* will write at the addresses via spapr_msi_write().
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*/
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static void spapr_msi_setmsg(PCIDevice *pdev, target_phys_addr_t addr,
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bool msix, unsigned req_num)
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{
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unsigned i;
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MSIMessage msg = { .address = addr, .data = 0 };
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if (!msix) {
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msi_set_message(pdev, msg);
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trace_spapr_pci_msi_setup(pdev->name, 0, msg.address);
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return;
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}
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for (i = 0; i < req_num; ++i) {
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msg.address = addr | (i << 2);
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msix_set_message(pdev, i, msg);
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trace_spapr_pci_msi_setup(pdev->name, i, msg.address);
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}
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}
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static void rtas_ibm_change_msi(sPAPREnvironment *spapr,
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uint32_t token, uint32_t nargs,
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target_ulong args, uint32_t nret,
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target_ulong rets)
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{
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uint32_t config_addr = rtas_ld(args, 0);
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uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
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unsigned int func = rtas_ld(args, 3);
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unsigned int req_num = rtas_ld(args, 4); /* 0 == remove all */
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unsigned int seq_num = rtas_ld(args, 5);
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unsigned int ret_intr_type;
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int ndev, irq;
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sPAPRPHBState *phb = NULL;
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PCIDevice *pdev = NULL;
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switch (func) {
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case RTAS_CHANGE_MSI_FN:
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case RTAS_CHANGE_FN:
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ret_intr_type = RTAS_TYPE_MSI;
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break;
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case RTAS_CHANGE_MSIX_FN:
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ret_intr_type = RTAS_TYPE_MSIX;
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break;
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default:
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fprintf(stderr, "rtas_ibm_change_msi(%u) is not implemented\n", func);
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rtas_st(rets, 0, -3); /* Parameter error */
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return;
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}
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/* Fins sPAPRPHBState */
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phb = find_phb(spapr, buid);
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if (phb) {
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pdev = find_dev(spapr, buid, config_addr);
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}
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if (!phb || !pdev) {
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rtas_st(rets, 0, -3); /* Parameter error */
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return;
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}
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/* Releasing MSIs */
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if (!req_num) {
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ndev = spapr_msicfg_find(phb, config_addr, false);
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if (ndev < 0) {
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trace_spapr_pci_msi("MSI has not been enabled", -1, config_addr);
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rtas_st(rets, 0, -1); /* Hardware error */
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return;
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}
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trace_spapr_pci_msi("Released MSIs", ndev, config_addr);
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rtas_st(rets, 0, 0);
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rtas_st(rets, 1, 0);
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return;
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}
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/* Enabling MSI */
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/* Find a device number in the map to add or reuse the existing one */
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ndev = spapr_msicfg_find(phb, config_addr, true);
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if (ndev >= SPAPR_MSIX_MAX_DEVS || ndev < 0) {
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fprintf(stderr, "No free entry for a new MSI device\n");
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rtas_st(rets, 0, -1); /* Hardware error */
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return;
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}
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trace_spapr_pci_msi("Configuring MSI", ndev, config_addr);
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/* Check if there is an old config and MSI number has not changed */
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if (phb->msi_table[ndev].nvec && (req_num != phb->msi_table[ndev].nvec)) {
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/* Unexpected behaviour */
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fprintf(stderr, "Cannot reuse MSI config for device#%d", ndev);
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rtas_st(rets, 0, -1); /* Hardware error */
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return;
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}
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/* There is no cached config, allocate MSIs */
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if (!phb->msi_table[ndev].nvec) {
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irq = spapr_allocate_irq_block(req_num, true);
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if (irq < 0) {
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fprintf(stderr, "Cannot allocate MSIs for device#%d", ndev);
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rtas_st(rets, 0, -1); /* Hardware error */
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return;
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}
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phb->msi_table[ndev].irq = irq;
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phb->msi_table[ndev].nvec = req_num;
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phb->msi_table[ndev].config_addr = config_addr;
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}
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/* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */
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spapr_msi_setmsg(pdev, phb->msi_win_addr | (ndev << 16),
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ret_intr_type == RTAS_TYPE_MSIX, req_num);
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rtas_st(rets, 0, 0);
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rtas_st(rets, 1, req_num);
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rtas_st(rets, 2, ++seq_num);
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rtas_st(rets, 3, ret_intr_type);
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trace_spapr_pci_rtas_ibm_change_msi(func, req_num);
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}
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static void rtas_ibm_query_interrupt_source_number(sPAPREnvironment *spapr,
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uint32_t token,
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uint32_t nargs,
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target_ulong args,
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uint32_t nret,
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target_ulong rets)
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{
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uint32_t config_addr = rtas_ld(args, 0);
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uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
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unsigned int intr_src_num = -1, ioa_intr_num = rtas_ld(args, 3);
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int ndev;
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sPAPRPHBState *phb = NULL;
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/* Fins sPAPRPHBState */
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phb = find_phb(spapr, buid);
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if (!phb) {
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rtas_st(rets, 0, -3); /* Parameter error */
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return;
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}
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/* Find device descriptor and start IRQ */
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ndev = spapr_msicfg_find(phb, config_addr, false);
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if (ndev < 0) {
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trace_spapr_pci_msi("MSI has not been enabled", -1, config_addr);
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rtas_st(rets, 0, -1); /* Hardware error */
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return;
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}
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intr_src_num = phb->msi_table[ndev].irq + ioa_intr_num;
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trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num,
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intr_src_num);
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rtas_st(rets, 0, 0);
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rtas_st(rets, 1, intr_src_num);
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rtas_st(rets, 2, 1);/* 0 == level; 1 == edge */
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}
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static int pci_spapr_swizzle(int slot, int pin)
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{
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return (slot + pin) % PCI_NUM_PINS;
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}
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static int pci_spapr_map_irq(PCIDevice *pci_dev, int irq_num)
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{
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/*
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* Here we need to convert pci_dev + irq_num to some unique value
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* which is less than number of IRQs on the specific bus (4). We
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* use standard PCI swizzling, that is (slot number + pin number)
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* % 4.
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*/
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return pci_spapr_swizzle(PCI_SLOT(pci_dev->devfn), irq_num);
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}
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static void pci_spapr_set_irq(void *opaque, int irq_num, int level)
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{
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/*
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* Here we use the number returned by pci_spapr_map_irq to find a
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* corresponding qemu_irq.
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*/
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sPAPRPHBState *phb = opaque;
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trace_spapr_pci_lsi_set(phb->busname, irq_num, phb->lsi_table[irq_num].irq);
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qemu_set_irq(spapr_phb_lsi_qirq(phb, irq_num), level);
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}
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static uint64_t spapr_io_read(void *opaque, target_phys_addr_t addr,
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unsigned size)
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{
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switch (size) {
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case 1:
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return cpu_inb(addr);
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case 2:
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return cpu_inw(addr);
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case 4:
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return cpu_inl(addr);
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}
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assert(0);
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}
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static void spapr_io_write(void *opaque, target_phys_addr_t addr,
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uint64_t data, unsigned size)
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{
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switch (size) {
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case 1:
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cpu_outb(addr, data);
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return;
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case 2:
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cpu_outw(addr, data);
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return;
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case 4:
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cpu_outl(addr, data);
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return;
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}
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assert(0);
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}
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static const MemoryRegionOps spapr_io_ops = {
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.endianness = DEVICE_LITTLE_ENDIAN,
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.read = spapr_io_read,
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.write = spapr_io_write
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};
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/*
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* MSI/MSIX memory region implementation.
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* The handler handles both MSI and MSIX.
|
|
* For MSI-X, the vector number is encoded as a part of the address,
|
|
* data is set to 0.
|
|
* For MSI, the vector number is encoded in least bits in data.
|
|
*/
|
|
static void spapr_msi_write(void *opaque, target_phys_addr_t addr,
|
|
uint64_t data, unsigned size)
|
|
{
|
|
sPAPRPHBState *phb = opaque;
|
|
int ndev = addr >> 16;
|
|
int vec = ((addr & 0xFFFF) >> 2) | data;
|
|
uint32_t irq = phb->msi_table[ndev].irq + vec;
|
|
|
|
trace_spapr_pci_msi_write(addr, data, irq);
|
|
|
|
qemu_irq_pulse(xics_get_qirq(spapr->icp, irq));
|
|
}
|
|
|
|
static const MemoryRegionOps spapr_msi_ops = {
|
|
/* There is no .read as the read result is undefined by PCI spec */
|
|
.read = NULL,
|
|
.write = spapr_msi_write,
|
|
.endianness = DEVICE_LITTLE_ENDIAN
|
|
};
|
|
|
|
/*
|
|
* PHB PCI device
|
|
*/
|
|
static DMAContext *spapr_pci_dma_context_fn(PCIBus *bus, void *opaque,
|
|
int devfn)
|
|
{
|
|
sPAPRPHBState *phb = opaque;
|
|
|
|
return phb->dma;
|
|
}
|
|
|
|
static int spapr_phb_init(SysBusDevice *s)
|
|
{
|
|
sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(s);
|
|
PCIHostState *phb = PCI_HOST_BRIDGE(s);
|
|
char *namebuf;
|
|
int i;
|
|
PCIBus *bus;
|
|
|
|
sphb->dtbusname = g_strdup_printf("pci@%" PRIx64, sphb->buid);
|
|
namebuf = alloca(strlen(sphb->dtbusname) + 32);
|
|
|
|
/* Initialize memory regions */
|
|
sprintf(namebuf, "%s.mmio", sphb->dtbusname);
|
|
memory_region_init(&sphb->memspace, namebuf, INT64_MAX);
|
|
|
|
sprintf(namebuf, "%s.mmio-alias", sphb->dtbusname);
|
|
memory_region_init_alias(&sphb->memwindow, namebuf, &sphb->memspace,
|
|
SPAPR_PCI_MEM_WIN_BUS_OFFSET, sphb->mem_win_size);
|
|
memory_region_add_subregion(get_system_memory(), sphb->mem_win_addr,
|
|
&sphb->memwindow);
|
|
|
|
/* On ppc, we only have MMIO no specific IO space from the CPU
|
|
* perspective. In theory we ought to be able to embed the PCI IO
|
|
* memory region direction in the system memory space. However,
|
|
* if any of the IO BAR subregions use the old_portio mechanism,
|
|
* that won't be processed properly unless accessed from the
|
|
* system io address space. This hack to bounce things via
|
|
* system_io works around the problem until all the users of
|
|
* old_portion are updated */
|
|
sprintf(namebuf, "%s.io", sphb->dtbusname);
|
|
memory_region_init(&sphb->iospace, namebuf, SPAPR_PCI_IO_WIN_SIZE);
|
|
/* FIXME: fix to support multiple PHBs */
|
|
memory_region_add_subregion(get_system_io(), 0, &sphb->iospace);
|
|
|
|
sprintf(namebuf, "%s.io-alias", sphb->dtbusname);
|
|
memory_region_init_io(&sphb->iowindow, &spapr_io_ops, sphb,
|
|
namebuf, SPAPR_PCI_IO_WIN_SIZE);
|
|
memory_region_add_subregion(get_system_memory(), sphb->io_win_addr,
|
|
&sphb->iowindow);
|
|
|
|
/* As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors,
|
|
* we need to allocate some memory to catch those writes coming
|
|
* from msi_notify()/msix_notify() */
|
|
if (msi_supported) {
|
|
sprintf(namebuf, "%s.msi", sphb->dtbusname);
|
|
memory_region_init_io(&sphb->msiwindow, &spapr_msi_ops, sphb,
|
|
namebuf, SPAPR_MSIX_MAX_DEVS * 0x10000);
|
|
memory_region_add_subregion(get_system_memory(), sphb->msi_win_addr,
|
|
&sphb->msiwindow);
|
|
}
|
|
|
|
bus = pci_register_bus(DEVICE(s),
|
|
sphb->busname ? sphb->busname : sphb->dtbusname,
|
|
pci_spapr_set_irq, pci_spapr_map_irq, sphb,
|
|
&sphb->memspace, &sphb->iospace,
|
|
PCI_DEVFN(0, 0), PCI_NUM_PINS);
|
|
phb->bus = bus;
|
|
|
|
sphb->dma_liobn = SPAPR_PCI_BASE_LIOBN | (pci_find_domain(bus) << 16);
|
|
sphb->dma_window_start = 0;
|
|
sphb->dma_window_size = 0x40000000;
|
|
sphb->dma = spapr_tce_new_dma_context(sphb->dma_liobn, sphb->dma_window_size);
|
|
pci_setup_iommu(bus, spapr_pci_dma_context_fn, sphb);
|
|
|
|
QLIST_INSERT_HEAD(&spapr->phbs, sphb, list);
|
|
|
|
/* Initialize the LSI table */
|
|
for (i = 0; i < PCI_NUM_PINS; i++) {
|
|
uint32_t irq;
|
|
|
|
irq = spapr_allocate_lsi(0);
|
|
if (!irq) {
|
|
return -1;
|
|
}
|
|
|
|
sphb->lsi_table[i].irq = irq;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void spapr_phb_reset(DeviceState *qdev)
|
|
{
|
|
SysBusDevice *s = sysbus_from_qdev(qdev);
|
|
sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(s);
|
|
|
|
/* Reset the IOMMU state */
|
|
spapr_tce_reset(sphb->dma);
|
|
}
|
|
|
|
static Property spapr_phb_properties[] = {
|
|
DEFINE_PROP_HEX64("buid", sPAPRPHBState, buid, 0),
|
|
DEFINE_PROP_STRING("busname", sPAPRPHBState, busname),
|
|
DEFINE_PROP_HEX64("mem_win_addr", sPAPRPHBState, mem_win_addr, 0),
|
|
DEFINE_PROP_HEX64("mem_win_size", sPAPRPHBState, mem_win_size, 0x20000000),
|
|
DEFINE_PROP_HEX64("io_win_addr", sPAPRPHBState, io_win_addr, 0),
|
|
DEFINE_PROP_HEX64("io_win_size", sPAPRPHBState, io_win_size, 0x10000),
|
|
DEFINE_PROP_HEX64("msi_win_addr", sPAPRPHBState, msi_win_addr, 0),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void spapr_phb_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
sdc->init = spapr_phb_init;
|
|
dc->props = spapr_phb_properties;
|
|
dc->reset = spapr_phb_reset;
|
|
}
|
|
|
|
static const TypeInfo spapr_phb_info = {
|
|
.name = TYPE_SPAPR_PCI_HOST_BRIDGE,
|
|
.parent = TYPE_PCI_HOST_BRIDGE,
|
|
.instance_size = sizeof(sPAPRPHBState),
|
|
.class_init = spapr_phb_class_init,
|
|
};
|
|
|
|
void spapr_create_phb(sPAPREnvironment *spapr,
|
|
const char *busname, uint64_t buid,
|
|
uint64_t mem_win_addr, uint64_t mem_win_size,
|
|
uint64_t io_win_addr, uint64_t msi_win_addr)
|
|
{
|
|
DeviceState *dev;
|
|
|
|
dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE);
|
|
|
|
if (busname) {
|
|
qdev_prop_set_string(dev, "busname", g_strdup(busname));
|
|
}
|
|
qdev_prop_set_uint64(dev, "buid", buid);
|
|
qdev_prop_set_uint64(dev, "mem_win_addr", mem_win_addr);
|
|
qdev_prop_set_uint64(dev, "mem_win_size", mem_win_size);
|
|
qdev_prop_set_uint64(dev, "io_win_addr", io_win_addr);
|
|
qdev_prop_set_uint64(dev, "msi_win_addr", msi_win_addr);
|
|
|
|
qdev_init_nofail(dev);
|
|
}
|
|
|
|
/* Macros to operate with address in OF binding to PCI */
|
|
#define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p))
|
|
#define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */
|
|
#define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */
|
|
#define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */
|
|
#define b_ss(x) b_x((x), 24, 2) /* the space code */
|
|
#define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */
|
|
#define b_ddddd(x) b_x((x), 11, 5) /* device number */
|
|
#define b_fff(x) b_x((x), 8, 3) /* function number */
|
|
#define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */
|
|
|
|
int spapr_populate_pci_dt(sPAPRPHBState *phb,
|
|
uint32_t xics_phandle,
|
|
void *fdt)
|
|
{
|
|
int bus_off, i, j;
|
|
char nodename[256];
|
|
uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) };
|
|
struct {
|
|
uint32_t hi;
|
|
uint64_t child;
|
|
uint64_t parent;
|
|
uint64_t size;
|
|
} QEMU_PACKED ranges[] = {
|
|
{
|
|
cpu_to_be32(b_ss(1)), cpu_to_be64(0),
|
|
cpu_to_be64(phb->io_win_addr),
|
|
cpu_to_be64(memory_region_size(&phb->iospace)),
|
|
},
|
|
{
|
|
cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET),
|
|
cpu_to_be64(phb->mem_win_addr),
|
|
cpu_to_be64(memory_region_size(&phb->memwindow)),
|
|
},
|
|
};
|
|
uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 };
|
|
uint32_t interrupt_map_mask[] = {
|
|
cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)};
|
|
uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7];
|
|
|
|
/* Start populating the FDT */
|
|
sprintf(nodename, "pci@%" PRIx64, phb->buid);
|
|
bus_off = fdt_add_subnode(fdt, 0, nodename);
|
|
if (bus_off < 0) {
|
|
return bus_off;
|
|
}
|
|
|
|
#define _FDT(exp) \
|
|
do { \
|
|
int ret = (exp); \
|
|
if (ret < 0) { \
|
|
return ret; \
|
|
} \
|
|
} while (0)
|
|
|
|
/* Write PHB properties */
|
|
_FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci"));
|
|
_FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB"));
|
|
_FDT(fdt_setprop_cell(fdt, bus_off, "#address-cells", 0x3));
|
|
_FDT(fdt_setprop_cell(fdt, bus_off, "#size-cells", 0x2));
|
|
_FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1));
|
|
_FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0));
|
|
_FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range)));
|
|
_FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof(ranges)));
|
|
_FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg)));
|
|
_FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1));
|
|
|
|
/* Build the interrupt-map, this must matches what is done
|
|
* in pci_spapr_map_irq
|
|
*/
|
|
_FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask",
|
|
&interrupt_map_mask, sizeof(interrupt_map_mask)));
|
|
for (i = 0; i < PCI_SLOT_MAX; i++) {
|
|
for (j = 0; j < PCI_NUM_PINS; j++) {
|
|
uint32_t *irqmap = interrupt_map[i*PCI_NUM_PINS + j];
|
|
int lsi_num = pci_spapr_swizzle(i, j);
|
|
|
|
irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0));
|
|
irqmap[1] = 0;
|
|
irqmap[2] = 0;
|
|
irqmap[3] = cpu_to_be32(j+1);
|
|
irqmap[4] = cpu_to_be32(xics_phandle);
|
|
irqmap[5] = cpu_to_be32(phb->lsi_table[lsi_num].irq);
|
|
irqmap[6] = cpu_to_be32(0x8);
|
|
}
|
|
}
|
|
/* Write interrupt map */
|
|
_FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map,
|
|
sizeof(interrupt_map)));
|
|
|
|
spapr_dma_dt(fdt, bus_off, "ibm,dma-window",
|
|
phb->dma_liobn, phb->dma_window_start,
|
|
phb->dma_window_size);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void spapr_pci_rtas_init(void)
|
|
{
|
|
spapr_rtas_register("read-pci-config", rtas_read_pci_config);
|
|
spapr_rtas_register("write-pci-config", rtas_write_pci_config);
|
|
spapr_rtas_register("ibm,read-pci-config", rtas_ibm_read_pci_config);
|
|
spapr_rtas_register("ibm,write-pci-config", rtas_ibm_write_pci_config);
|
|
if (msi_supported) {
|
|
spapr_rtas_register("ibm,query-interrupt-source-number",
|
|
rtas_ibm_query_interrupt_source_number);
|
|
spapr_rtas_register("ibm,change-msi", rtas_ibm_change_msi);
|
|
}
|
|
}
|
|
|
|
static void spapr_pci_register_types(void)
|
|
{
|
|
type_register_static(&spapr_phb_info);
|
|
}
|
|
|
|
type_init(spapr_pci_register_types)
|