The ZynqMP contains two instances of a generic DMA, the GDMA, located in the FPD (full power domain), and the ADMA, located in LPD (low power domain). This patch adds these two DMAs to the ZynqMP board. Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20180503214201.29082-3-frasse.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
584 lines
20 KiB
C
584 lines
20 KiB
C
/*
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* Xilinx Zynq MPSoC emulation
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*
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* Copyright (C) 2015 Xilinx Inc
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* Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu-common.h"
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#include "cpu.h"
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#include "hw/arm/xlnx-zynqmp.h"
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#include "hw/intc/arm_gic_common.h"
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#include "exec/address-spaces.h"
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#include "sysemu/kvm.h"
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#include "kvm_arm.h"
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#define GIC_NUM_SPI_INTR 160
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#define ARM_PHYS_TIMER_PPI 30
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#define ARM_VIRT_TIMER_PPI 27
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#define GEM_REVISION 0x40070106
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#define GIC_BASE_ADDR 0xf9000000
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#define GIC_DIST_ADDR 0xf9010000
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#define GIC_CPU_ADDR 0xf9020000
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#define SATA_INTR 133
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#define SATA_ADDR 0xFD0C0000
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#define SATA_NUM_PORTS 2
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#define QSPI_ADDR 0xff0f0000
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#define LQSPI_ADDR 0xc0000000
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#define QSPI_IRQ 15
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#define DP_ADDR 0xfd4a0000
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#define DP_IRQ 113
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#define DPDMA_ADDR 0xfd4c0000
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#define DPDMA_IRQ 116
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#define IPI_ADDR 0xFF300000
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#define IPI_IRQ 64
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#define RTC_ADDR 0xffa60000
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#define RTC_IRQ 26
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#define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */
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static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
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0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
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};
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static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = {
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57, 59, 61, 63,
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};
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static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = {
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0xFF000000, 0xFF010000,
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};
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static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
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21, 22,
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};
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static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = {
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0xFF160000, 0xFF170000,
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};
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static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = {
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48, 49,
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};
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static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = {
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0xFF040000, 0xFF050000,
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};
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static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = {
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19, 20,
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};
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static const uint64_t gdma_ch_addr[XLNX_ZYNQMP_NUM_GDMA_CH] = {
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0xFD500000, 0xFD510000, 0xFD520000, 0xFD530000,
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0xFD540000, 0xFD550000, 0xFD560000, 0xFD570000
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};
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static const int gdma_ch_intr[XLNX_ZYNQMP_NUM_GDMA_CH] = {
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124, 125, 126, 127, 128, 129, 130, 131
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};
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static const uint64_t adma_ch_addr[XLNX_ZYNQMP_NUM_ADMA_CH] = {
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0xFFA80000, 0xFFA90000, 0xFFAA0000, 0xFFAB0000,
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0xFFAC0000, 0xFFAD0000, 0xFFAE0000, 0xFFAF0000
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};
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static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH] = {
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77, 78, 79, 80, 81, 82, 83, 84
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};
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typedef struct XlnxZynqMPGICRegion {
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int region_index;
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uint32_t address;
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} XlnxZynqMPGICRegion;
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static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = {
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{ .region_index = 0, .address = GIC_DIST_ADDR, },
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{ .region_index = 1, .address = GIC_CPU_ADDR, },
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};
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static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
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{
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return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
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}
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static void xlnx_zynqmp_create_rpu(XlnxZynqMPState *s, const char *boot_cpu,
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Error **errp)
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{
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Error *err = NULL;
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int i;
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int num_rpus = MIN(smp_cpus - XLNX_ZYNQMP_NUM_APU_CPUS, XLNX_ZYNQMP_NUM_RPU_CPUS);
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for (i = 0; i < num_rpus; i++) {
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char *name;
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object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]),
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"cortex-r5-" TYPE_ARM_CPU);
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object_property_add_child(OBJECT(s), "rpu-cpu[*]",
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OBJECT(&s->rpu_cpu[i]), &error_abort);
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name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i]));
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if (strcmp(name, boot_cpu)) {
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/* Secondary CPUs start in PSCI powered-down state */
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object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true,
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"start-powered-off", &error_abort);
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} else {
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s->boot_cpu_ptr = &s->rpu_cpu[i];
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}
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g_free(name);
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object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs",
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&error_abort);
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object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized",
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&err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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}
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}
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static void xlnx_zynqmp_init(Object *obj)
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{
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XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
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int i;
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int num_apus = MIN(smp_cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
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for (i = 0; i < num_apus; i++) {
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object_initialize(&s->apu_cpu[i], sizeof(s->apu_cpu[i]),
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"cortex-a53-" TYPE_ARM_CPU);
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object_property_add_child(obj, "apu-cpu[*]", OBJECT(&s->apu_cpu[i]),
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&error_abort);
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}
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object_initialize(&s->gic, sizeof(s->gic), gic_class_name());
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qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
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for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
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object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM);
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qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default());
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}
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for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
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object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART);
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qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
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}
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object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI);
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qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default());
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for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
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object_initialize(&s->sdhci[i], sizeof(s->sdhci[i]),
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TYPE_SYSBUS_SDHCI);
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qdev_set_parent_bus(DEVICE(&s->sdhci[i]),
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sysbus_get_default());
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}
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for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
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object_initialize(&s->spi[i], sizeof(s->spi[i]),
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TYPE_XILINX_SPIPS);
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qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
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}
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object_initialize(&s->qspi, sizeof(s->qspi), TYPE_XLNX_ZYNQMP_QSPIPS);
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qdev_set_parent_bus(DEVICE(&s->qspi), sysbus_get_default());
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object_initialize(&s->dp, sizeof(s->dp), TYPE_XLNX_DP);
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qdev_set_parent_bus(DEVICE(&s->dp), sysbus_get_default());
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object_initialize(&s->dpdma, sizeof(s->dpdma), TYPE_XLNX_DPDMA);
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qdev_set_parent_bus(DEVICE(&s->dpdma), sysbus_get_default());
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object_initialize(&s->ipi, sizeof(s->ipi), TYPE_XLNX_ZYNQMP_IPI);
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qdev_set_parent_bus(DEVICE(&s->ipi), sysbus_get_default());
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object_initialize(&s->rtc, sizeof(s->rtc), TYPE_XLNX_ZYNQMP_RTC);
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qdev_set_parent_bus(DEVICE(&s->rtc), sysbus_get_default());
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for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
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object_initialize(&s->gdma[i], sizeof(s->gdma[i]), TYPE_XLNX_ZDMA);
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qdev_set_parent_bus(DEVICE(&s->gdma[i]), sysbus_get_default());
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}
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for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) {
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object_initialize(&s->adma[i], sizeof(s->adma[i]), TYPE_XLNX_ZDMA);
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qdev_set_parent_bus(DEVICE(&s->adma[i]), sysbus_get_default());
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}
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}
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static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
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{
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XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
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MemoryRegion *system_memory = get_system_memory();
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uint8_t i;
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uint64_t ram_size;
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int num_apus = MIN(smp_cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
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const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]";
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ram_addr_t ddr_low_size, ddr_high_size;
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qemu_irq gic_spi[GIC_NUM_SPI_INTR];
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Error *err = NULL;
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ram_size = memory_region_size(s->ddr_ram);
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/* Create the DDR Memory Regions. User friendly checks should happen at
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* the board level
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*/
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if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) {
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/* The RAM size is above the maximum available for the low DDR.
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* Create the high DDR memory region as well.
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*/
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assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE);
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ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
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ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
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memory_region_init_alias(&s->ddr_ram_high, NULL,
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"ddr-ram-high", s->ddr_ram,
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ddr_low_size, ddr_high_size);
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memory_region_add_subregion(get_system_memory(),
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XLNX_ZYNQMP_HIGH_RAM_START,
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&s->ddr_ram_high);
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} else {
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/* RAM must be non-zero */
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assert(ram_size);
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ddr_low_size = ram_size;
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}
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memory_region_init_alias(&s->ddr_ram_low, NULL,
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"ddr-ram-low", s->ddr_ram,
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0, ddr_low_size);
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memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low);
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/* Create the four OCM banks */
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for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) {
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char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i);
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memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name,
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XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal);
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memory_region_add_subregion(get_system_memory(),
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XLNX_ZYNQMP_OCM_RAM_0_ADDRESS +
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i * XLNX_ZYNQMP_OCM_RAM_SIZE,
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&s->ocm_ram[i]);
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g_free(ocm_name);
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}
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qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
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qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
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qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus);
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/* Realize APUs before realizing the GIC. KVM requires this. */
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for (i = 0; i < num_apus; i++) {
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char *name;
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object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC,
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"psci-conduit", &error_abort);
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name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i]));
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if (strcmp(name, boot_cpu)) {
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/* Secondary CPUs start in PSCI powered-down state */
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object_property_set_bool(OBJECT(&s->apu_cpu[i]), true,
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"start-powered-off", &error_abort);
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} else {
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s->boot_cpu_ptr = &s->apu_cpu[i];
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}
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g_free(name);
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object_property_set_bool(OBJECT(&s->apu_cpu[i]),
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s->secure, "has_el3", NULL);
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object_property_set_bool(OBJECT(&s->apu_cpu[i]),
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s->virt, "has_el2", NULL);
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object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR,
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"reset-cbar", &error_abort);
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object_property_set_int(OBJECT(&s->apu_cpu[i]), num_apus,
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"core-count", &error_abort);
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object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized",
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&err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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}
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object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS);
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for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) {
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SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic);
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const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i];
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MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index);
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uint32_t addr = r->address;
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int j;
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sysbus_mmio_map(gic, r->region_index, addr);
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for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) {
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MemoryRegion *alias = &s->gic_mr[i][j];
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addr += XLNX_ZYNQMP_GIC_REGION_SIZE;
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memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr,
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0, XLNX_ZYNQMP_GIC_REGION_SIZE);
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memory_region_add_subregion(system_memory, addr, alias);
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}
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}
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for (i = 0; i < num_apus; i++) {
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qemu_irq irq;
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
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qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
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ARM_CPU_IRQ));
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irq = qdev_get_gpio_in(DEVICE(&s->gic),
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arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
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qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 0, irq);
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irq = qdev_get_gpio_in(DEVICE(&s->gic),
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arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
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qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq);
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}
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if (s->has_rpu) {
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info_report("The 'has_rpu' property is no longer required, to use the "
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"RPUs just use -smp 6.");
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}
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xlnx_zynqmp_create_rpu(s, boot_cpu, &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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if (!s->boot_cpu_ptr) {
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error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu);
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return;
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}
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for (i = 0; i < GIC_NUM_SPI_INTR; i++) {
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gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
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}
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for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
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NICInfo *nd = &nd_table[i];
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if (nd->used) {
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qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
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qdev_set_nic_properties(DEVICE(&s->gem[i]), nd);
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}
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object_property_set_int(OBJECT(&s->gem[i]), GEM_REVISION, "revision",
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&error_abort);
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object_property_set_int(OBJECT(&s->gem[i]), 2, "num-priority-queues",
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&error_abort);
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object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0,
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gic_spi[gem_intr[i]]);
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}
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for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
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qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
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object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
|
|
gic_spi[uart_intr[i]]);
|
|
}
|
|
|
|
object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports",
|
|
&error_abort);
|
|
object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
|
|
if (err) {
|
|
error_propagate(errp, err);
|
|
return;
|
|
}
|
|
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);
|
|
|
|
for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
|
|
char *bus_name = g_strdup_printf("sd-bus%d", i);
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sdhci[i]);
|
|
Object *sdhci = OBJECT(&s->sdhci[i]);
|
|
|
|
/* Compatible with:
|
|
* - SD Host Controller Specification Version 3.00
|
|
* - SDIO Specification Version 3.0
|
|
* - eMMC Specification Version 4.51
|
|
*/
|
|
object_property_set_uint(sdhci, 3, "sd-spec-version", &err);
|
|
object_property_set_uint(sdhci, SDHCI_CAPABILITIES, "capareg", &err);
|
|
object_property_set_uint(sdhci, UHS_I, "uhs", &err);
|
|
object_property_set_bool(sdhci, true, "realized", &err);
|
|
if (err) {
|
|
error_propagate(errp, err);
|
|
return;
|
|
}
|
|
sysbus_mmio_map(sbd, 0, sdhci_addr[i]);
|
|
sysbus_connect_irq(sbd, 0, gic_spi[sdhci_intr[i]]);
|
|
|
|
/* Alias controller SD bus to the SoC itself */
|
|
object_property_add_alias(OBJECT(s), bus_name, sdhci, "sd-bus",
|
|
&error_abort);
|
|
g_free(bus_name);
|
|
}
|
|
|
|
for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
|
|
gchar *bus_name;
|
|
|
|
object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
|
|
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
|
|
gic_spi[spi_intr[i]]);
|
|
|
|
/* Alias controller SPI bus to the SoC itself */
|
|
bus_name = g_strdup_printf("spi%d", i);
|
|
object_property_add_alias(OBJECT(s), bus_name,
|
|
OBJECT(&s->spi[i]), "spi0",
|
|
&error_abort);
|
|
g_free(bus_name);
|
|
}
|
|
|
|
object_property_set_bool(OBJECT(&s->qspi), true, "realized", &err);
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR);
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, gic_spi[QSPI_IRQ]);
|
|
|
|
for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) {
|
|
gchar *bus_name;
|
|
gchar *target_bus;
|
|
|
|
/* Alias controller SPI bus to the SoC itself */
|
|
bus_name = g_strdup_printf("qspi%d", i);
|
|
target_bus = g_strdup_printf("spi%d", i);
|
|
object_property_add_alias(OBJECT(s), bus_name,
|
|
OBJECT(&s->qspi), target_bus,
|
|
&error_abort);
|
|
g_free(bus_name);
|
|
g_free(target_bus);
|
|
}
|
|
|
|
object_property_set_bool(OBJECT(&s->dp), true, "realized", &err);
|
|
if (err) {
|
|
error_propagate(errp, err);
|
|
return;
|
|
}
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]);
|
|
|
|
object_property_set_bool(OBJECT(&s->dpdma), true, "realized", &err);
|
|
if (err) {
|
|
error_propagate(errp, err);
|
|
return;
|
|
}
|
|
object_property_set_link(OBJECT(&s->dp), OBJECT(&s->dpdma), "dpdma",
|
|
&error_abort);
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]);
|
|
|
|
object_property_set_bool(OBJECT(&s->ipi), true, "realized", &err);
|
|
if (err) {
|
|
error_propagate(errp, err);
|
|
return;
|
|
}
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi), 0, IPI_ADDR);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi), 0, gic_spi[IPI_IRQ]);
|
|
|
|
object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
|
|
if (err) {
|
|
error_propagate(errp, err);
|
|
return;
|
|
}
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]);
|
|
|
|
for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
|
|
object_property_set_uint(OBJECT(&s->gdma[i]), 128, "bus-width", &err);
|
|
object_property_set_bool(OBJECT(&s->gdma[i]), true, "realized", &err);
|
|
if (err) {
|
|
error_propagate(errp, err);
|
|
return;
|
|
}
|
|
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gdma[i]), 0, gdma_ch_addr[i]);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gdma[i]), 0,
|
|
gic_spi[gdma_ch_intr[i]]);
|
|
}
|
|
|
|
for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) {
|
|
object_property_set_bool(OBJECT(&s->adma[i]), true, "realized", &err);
|
|
if (err) {
|
|
error_propagate(errp, err);
|
|
return;
|
|
}
|
|
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->adma[i]), 0, adma_ch_addr[i]);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->adma[i]), 0,
|
|
gic_spi[adma_ch_intr[i]]);
|
|
}
|
|
}
|
|
|
|
static Property xlnx_zynqmp_props[] = {
|
|
DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu),
|
|
DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false),
|
|
DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false),
|
|
DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false),
|
|
DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION,
|
|
MemoryRegion *),
|
|
DEFINE_PROP_END_OF_LIST()
|
|
};
|
|
|
|
static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
dc->props = xlnx_zynqmp_props;
|
|
dc->realize = xlnx_zynqmp_realize;
|
|
/* Reason: Uses serial_hds in realize function, thus can't be used twice */
|
|
dc->user_creatable = false;
|
|
}
|
|
|
|
static const TypeInfo xlnx_zynqmp_type_info = {
|
|
.name = TYPE_XLNX_ZYNQMP,
|
|
.parent = TYPE_DEVICE,
|
|
.instance_size = sizeof(XlnxZynqMPState),
|
|
.instance_init = xlnx_zynqmp_init,
|
|
.class_init = xlnx_zynqmp_class_init,
|
|
};
|
|
|
|
static void xlnx_zynqmp_register_types(void)
|
|
{
|
|
type_register_static(&xlnx_zynqmp_type_info);
|
|
}
|
|
|
|
type_init(xlnx_zynqmp_register_types)
|