qemu-patch-raspberry4/target
Suraj Jitindar Singh 072f416a53 target/ppc: Don't require private l1d cache on POWER8 for cap_ppc_safe_cache
For cap_ppc_safe_cache to be set to workaround, we require both a l1d
cache flush instruction and private l1d cache.

On POWER8 don't require private l1d cache. This means a guest on a
POWER8 machine can make use of the cache flush workarounds.

Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-06-16 16:32:33 +10:00
..
alpha tcg: Pass tb and index to tcg_gen_exit_tb separately 2018-06-01 15:15:27 -07:00
arm target/arm: Allow ARMv6-M Thumb2 instructions 2018-06-15 15:23:34 +01:00
cris tcg-next queue 2018-06-04 11:28:31 +01:00
hppa tcg-next queue 2018-06-04 11:28:31 +01:00
i386 i386: Populate AMD Processor Cache Information for cpuid 0x8000001D 2018-06-08 15:54:10 -03:00
lm32 tcg-next queue 2018-06-04 11:28:31 +01:00
m68k target/m68k: Merge disas_m68k_insn into m68k_tr_translate_insn 2018-06-11 12:43:42 +02:00
microblaze target-microblaze: Rework NOP/zero instruction handling 2018-06-15 09:05:00 +02:00
mips tcg: Pass tb and index to tcg_gen_exit_tb separately 2018-06-01 15:15:27 -07:00
moxie tcg-next queue 2018-06-04 11:28:31 +01:00
nios2 tcg-next queue 2018-06-04 11:28:31 +01:00
openrisc tcg-next queue 2018-06-04 11:28:31 +01:00
ppc target/ppc: Don't require private l1d cache on POWER8 for cap_ppc_safe_cache 2018-06-16 16:32:33 +10:00
riscv RISC-V: Add trailing '\n' to qemu_log() calls 2018-06-08 13:15:33 +01:00
s390x tcg-next queue 2018-06-04 11:28:31 +01:00
sh4 tcg: Pass tb and index to tcg_gen_exit_tb separately 2018-06-01 15:15:27 -07:00
sparc move more data to arch specific files 2018-06-05 10:38:33 +01:00
tilegx tcg-next queue 2018-06-04 11:28:31 +01:00
tricore tcg: Pass tb and index to tcg_gen_exit_tb separately 2018-06-01 15:15:27 -07:00
unicore32 tcg: Pass tb and index to tcg_gen_exit_tb separately 2018-06-01 15:15:27 -07:00
xtensa target/xtensa: Add trailing '\n' to qemu_log() calls 2018-06-08 13:15:33 +01:00