Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-47-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
57 lines
2.3 KiB
Plaintext
57 lines
2.3 KiB
Plaintext
# Thumb1 instructions
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#
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# Copyright (c) 2019 Linaro, Ltd
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#
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# This library is free software; you can redistribute it and/or
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# modify it under the terms of the GNU Lesser General Public
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# License as published by the Free Software Foundation; either
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# version 2 of the License, or (at your option) any later version.
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#
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# This library is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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# Lesser General Public License for more details.
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#
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# You should have received a copy of the GNU Lesser General Public
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# License along with this library; if not, see <http://www.gnu.org/licenses/>.
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#
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# This file is processed by scripts/decodetree.py
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#
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&s_rrr_shi !extern s rd rn rm shim shty
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&s_rrr_shr !extern s rn rd rm rs shty
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&s_rri_rot !extern s rn rd imm rot
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&s_rrrr !extern s rd rn rm ra
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# Set S if the instruction is outside of an IT block.
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%s !function=t16_setflags
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# Data-processing (two low registers)
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%reg_0 0:3
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@lll_noshr ...... .... rm:3 rd:3 \
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&s_rrr_shi %s rn=%reg_0 shim=0 shty=0
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@xll_noshr ...... .... rm:3 rn:3 \
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&s_rrr_shi s=1 rd=0 shim=0 shty=0
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@lxl_shr ...... .... rs:3 rd:3 \
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&s_rrr_shr %s rm=%reg_0 rn=0
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AND_rrri 010000 0000 ... ... @lll_noshr
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EOR_rrri 010000 0001 ... ... @lll_noshr
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MOV_rxrr 010000 0010 ... ... @lxl_shr shty=0 # LSL
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MOV_rxrr 010000 0011 ... ... @lxl_shr shty=1 # LSR
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MOV_rxrr 010000 0100 ... ... @lxl_shr shty=2 # ASR
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ADC_rrri 010000 0101 ... ... @lll_noshr
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SBC_rrri 010000 0110 ... ... @lll_noshr
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MOV_rxrr 010000 0111 ... ... @lxl_shr shty=3 # ROR
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TST_xrri 010000 1000 ... ... @xll_noshr
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RSB_rri 010000 1001 rn:3 rd:3 &s_rri_rot %s imm=0 rot=0
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CMP_xrri 010000 1010 ... ... @xll_noshr
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CMN_xrri 010000 1011 ... ... @xll_noshr
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ORR_rrri 010000 1100 ... ... @lll_noshr
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MUL 010000 1101 rn:3 rd:3 &s_rrrr %s rm=%reg_0 ra=0
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BIC_rrri 010000 1110 ... ... @lll_noshr
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MVN_rxri 010000 1111 ... ... @lll_noshr
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