Move the reset value of SCTLR to ARMCPU, initialised in the per-cpu init functions. It can then be reset by a simple copy, and we can drop the code from cpu_reset_model_id(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Andreas Färber <afaerber@suse.de>
485 lines
14 KiB
C
485 lines
14 KiB
C
/*
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* QEMU ARM CPU
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*
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see
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* <http://www.gnu.org/licenses/gpl-2.0.html>
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*/
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#include "cpu-qom.h"
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#include "qemu-common.h"
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/* CPUClass::reset() */
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static void arm_cpu_reset(CPUState *s)
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{
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ARMCPU *cpu = ARM_CPU(s);
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ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
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acc->parent_reset(s);
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/* TODO Inline the current contents of cpu_state_reset(),
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once cpu_reset_model_id() is eliminated. */
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cpu_state_reset(&cpu->env);
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}
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static inline void set_feature(CPUARMState *env, int feature)
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{
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env->features |= 1u << feature;
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}
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static void arm_cpu_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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cpu_exec_init(&cpu->env);
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}
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void arm_cpu_realize(ARMCPU *cpu)
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{
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/* This function is called by cpu_arm_init() because it
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* needs to do common actions based on feature bits, etc
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* that have been set by the subclass init functions.
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* When we have QOM realize support it should become
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* a true realize function instead.
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*/
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CPUARMState *env = &cpu->env;
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/* Some features automatically imply others: */
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if (arm_feature(env, ARM_FEATURE_V7)) {
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set_feature(env, ARM_FEATURE_VAPA);
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set_feature(env, ARM_FEATURE_THUMB2);
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if (!arm_feature(env, ARM_FEATURE_M)) {
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set_feature(env, ARM_FEATURE_V6K);
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} else {
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set_feature(env, ARM_FEATURE_V6);
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}
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}
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if (arm_feature(env, ARM_FEATURE_V6K)) {
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set_feature(env, ARM_FEATURE_V6);
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set_feature(env, ARM_FEATURE_MVFR);
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}
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if (arm_feature(env, ARM_FEATURE_V6)) {
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set_feature(env, ARM_FEATURE_V5);
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if (!arm_feature(env, ARM_FEATURE_M)) {
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set_feature(env, ARM_FEATURE_AUXCR);
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}
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}
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if (arm_feature(env, ARM_FEATURE_V5)) {
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set_feature(env, ARM_FEATURE_V4T);
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}
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if (arm_feature(env, ARM_FEATURE_M)) {
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set_feature(env, ARM_FEATURE_THUMB_DIV);
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}
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if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
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set_feature(env, ARM_FEATURE_THUMB_DIV);
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}
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if (arm_feature(env, ARM_FEATURE_VFP4)) {
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set_feature(env, ARM_FEATURE_VFP3);
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}
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if (arm_feature(env, ARM_FEATURE_VFP3)) {
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set_feature(env, ARM_FEATURE_VFP);
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}
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}
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/* CPU models */
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static void arm926_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V5);
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set_feature(&cpu->env, ARM_FEATURE_VFP);
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cpu->midr = ARM_CPUID_ARM926;
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cpu->reset_fpsid = 0x41011090;
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cpu->ctr = 0x1dd20d2;
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cpu->reset_sctlr = 0x00090078;
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}
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static void arm946_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V5);
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set_feature(&cpu->env, ARM_FEATURE_MPU);
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cpu->midr = ARM_CPUID_ARM946;
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cpu->ctr = 0x0f004006;
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cpu->reset_sctlr = 0x00000078;
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}
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static void arm1026_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V5);
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set_feature(&cpu->env, ARM_FEATURE_VFP);
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set_feature(&cpu->env, ARM_FEATURE_AUXCR);
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cpu->midr = ARM_CPUID_ARM1026;
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cpu->reset_fpsid = 0x410110a0;
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cpu->ctr = 0x1dd20d2;
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cpu->reset_sctlr = 0x00090078;
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}
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static void arm1136_r2_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V6);
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set_feature(&cpu->env, ARM_FEATURE_VFP);
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cpu->midr = ARM_CPUID_ARM1136_R2;
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cpu->reset_fpsid = 0x410120b4;
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cpu->mvfr0 = 0x11111111;
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cpu->mvfr1 = 0x00000000;
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cpu->ctr = 0x1dd20d2;
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cpu->reset_sctlr = 0x00050078;
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}
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static void arm1136_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V6K);
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set_feature(&cpu->env, ARM_FEATURE_V6);
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set_feature(&cpu->env, ARM_FEATURE_VFP);
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cpu->midr = ARM_CPUID_ARM1136;
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cpu->reset_fpsid = 0x410120b4;
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cpu->mvfr0 = 0x11111111;
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cpu->mvfr1 = 0x00000000;
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cpu->ctr = 0x1dd20d2;
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cpu->reset_sctlr = 0x00050078;
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}
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static void arm1176_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V6K);
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set_feature(&cpu->env, ARM_FEATURE_VFP);
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set_feature(&cpu->env, ARM_FEATURE_VAPA);
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cpu->midr = ARM_CPUID_ARM1176;
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cpu->reset_fpsid = 0x410120b5;
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cpu->mvfr0 = 0x11111111;
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cpu->mvfr1 = 0x00000000;
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cpu->ctr = 0x1dd20d2;
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cpu->reset_sctlr = 0x00050078;
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}
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static void arm11mpcore_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V6K);
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set_feature(&cpu->env, ARM_FEATURE_VFP);
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set_feature(&cpu->env, ARM_FEATURE_VAPA);
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cpu->midr = ARM_CPUID_ARM11MPCORE;
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cpu->reset_fpsid = 0x410120b4;
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cpu->mvfr0 = 0x11111111;
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cpu->mvfr1 = 0x00000000;
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cpu->ctr = 0x1dd20d2;
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}
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static void cortex_m3_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V7);
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set_feature(&cpu->env, ARM_FEATURE_M);
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cpu->midr = ARM_CPUID_CORTEXM3;
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}
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static void cortex_a8_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V7);
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set_feature(&cpu->env, ARM_FEATURE_VFP3);
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set_feature(&cpu->env, ARM_FEATURE_NEON);
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set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
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cpu->midr = ARM_CPUID_CORTEXA8;
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cpu->reset_fpsid = 0x410330c0;
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cpu->mvfr0 = 0x11110222;
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cpu->mvfr1 = 0x00011100;
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cpu->ctr = 0x82048004;
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cpu->reset_sctlr = 0x00c50078;
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}
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static void cortex_a9_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V7);
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set_feature(&cpu->env, ARM_FEATURE_VFP3);
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set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
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set_feature(&cpu->env, ARM_FEATURE_NEON);
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set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
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/* Note that A9 supports the MP extensions even for
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* A9UP and single-core A9MP (which are both different
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* and valid configurations; we don't model A9UP).
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*/
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set_feature(&cpu->env, ARM_FEATURE_V7MP);
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cpu->midr = ARM_CPUID_CORTEXA9;
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cpu->reset_fpsid = 0x41033090;
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cpu->mvfr0 = 0x11110222;
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cpu->mvfr1 = 0x01111111;
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cpu->ctr = 0x80038003;
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cpu->reset_sctlr = 0x00c50078;
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}
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static void cortex_a15_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V7);
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set_feature(&cpu->env, ARM_FEATURE_VFP4);
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set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
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set_feature(&cpu->env, ARM_FEATURE_NEON);
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set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
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set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
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set_feature(&cpu->env, ARM_FEATURE_V7MP);
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set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
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cpu->midr = ARM_CPUID_CORTEXA15;
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cpu->reset_fpsid = 0x410430f0;
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cpu->mvfr0 = 0x10110222;
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cpu->mvfr1 = 0x11111111;
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cpu->ctr = 0x8444c004;
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cpu->reset_sctlr = 0x00c50078;
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}
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static void ti925t_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V4T);
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set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
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cpu->midr = ARM_CPUID_TI925T;
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cpu->ctr = 0x5109149;
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cpu->reset_sctlr = 0x00000070;
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}
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static void sa1100_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
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cpu->midr = ARM_CPUID_SA1100;
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cpu->reset_sctlr = 0x00000070;
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}
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static void sa1110_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
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cpu->midr = ARM_CPUID_SA1110;
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cpu->reset_sctlr = 0x00000070;
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}
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static void pxa250_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V5);
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set_feature(&cpu->env, ARM_FEATURE_XSCALE);
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cpu->midr = ARM_CPUID_PXA250;
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cpu->ctr = 0xd172172;
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cpu->reset_sctlr = 0x00000078;
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}
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static void pxa255_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V5);
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set_feature(&cpu->env, ARM_FEATURE_XSCALE);
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cpu->midr = ARM_CPUID_PXA255;
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cpu->ctr = 0xd172172;
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cpu->reset_sctlr = 0x00000078;
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}
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static void pxa260_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V5);
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set_feature(&cpu->env, ARM_FEATURE_XSCALE);
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cpu->midr = ARM_CPUID_PXA260;
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cpu->ctr = 0xd172172;
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cpu->reset_sctlr = 0x00000078;
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}
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static void pxa261_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V5);
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set_feature(&cpu->env, ARM_FEATURE_XSCALE);
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cpu->midr = ARM_CPUID_PXA261;
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cpu->ctr = 0xd172172;
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cpu->reset_sctlr = 0x00000078;
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}
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static void pxa262_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V5);
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set_feature(&cpu->env, ARM_FEATURE_XSCALE);
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cpu->midr = ARM_CPUID_PXA262;
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cpu->ctr = 0xd172172;
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cpu->reset_sctlr = 0x00000078;
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}
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static void pxa270a0_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V5);
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set_feature(&cpu->env, ARM_FEATURE_XSCALE);
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set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
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cpu->midr = ARM_CPUID_PXA270_A0;
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cpu->ctr = 0xd172172;
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cpu->reset_sctlr = 0x00000078;
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}
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static void pxa270a1_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V5);
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set_feature(&cpu->env, ARM_FEATURE_XSCALE);
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set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
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cpu->midr = ARM_CPUID_PXA270_A1;
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cpu->ctr = 0xd172172;
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cpu->reset_sctlr = 0x00000078;
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}
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static void pxa270b0_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V5);
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set_feature(&cpu->env, ARM_FEATURE_XSCALE);
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set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
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cpu->midr = ARM_CPUID_PXA270_B0;
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cpu->ctr = 0xd172172;
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cpu->reset_sctlr = 0x00000078;
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}
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static void pxa270b1_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V5);
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set_feature(&cpu->env, ARM_FEATURE_XSCALE);
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set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
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cpu->midr = ARM_CPUID_PXA270_B1;
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cpu->ctr = 0xd172172;
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cpu->reset_sctlr = 0x00000078;
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}
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static void pxa270c0_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V5);
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set_feature(&cpu->env, ARM_FEATURE_XSCALE);
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set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
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cpu->midr = ARM_CPUID_PXA270_C0;
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cpu->ctr = 0xd172172;
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cpu->reset_sctlr = 0x00000078;
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}
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static void pxa270c5_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V5);
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set_feature(&cpu->env, ARM_FEATURE_XSCALE);
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set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
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cpu->midr = ARM_CPUID_PXA270_C5;
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cpu->ctr = 0xd172172;
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cpu->reset_sctlr = 0x00000078;
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}
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static void arm_any_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V7);
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set_feature(&cpu->env, ARM_FEATURE_VFP4);
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set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
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set_feature(&cpu->env, ARM_FEATURE_NEON);
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set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
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set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
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set_feature(&cpu->env, ARM_FEATURE_V7MP);
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cpu->midr = ARM_CPUID_ANY;
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}
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typedef struct ARMCPUInfo {
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const char *name;
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void (*initfn)(Object *obj);
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} ARMCPUInfo;
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static const ARMCPUInfo arm_cpus[] = {
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{ .name = "arm926", .initfn = arm926_initfn },
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{ .name = "arm946", .initfn = arm946_initfn },
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{ .name = "arm1026", .initfn = arm1026_initfn },
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/* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
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* older core than plain "arm1136". In particular this does not
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* have the v6K features.
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*/
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{ .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
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{ .name = "arm1136", .initfn = arm1136_initfn },
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{ .name = "arm1176", .initfn = arm1176_initfn },
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{ .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
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{ .name = "cortex-m3", .initfn = cortex_m3_initfn },
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{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
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{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
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{ .name = "cortex-a15", .initfn = cortex_a15_initfn },
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{ .name = "ti925t", .initfn = ti925t_initfn },
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{ .name = "sa1100", .initfn = sa1100_initfn },
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{ .name = "sa1110", .initfn = sa1110_initfn },
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{ .name = "pxa250", .initfn = pxa250_initfn },
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{ .name = "pxa255", .initfn = pxa255_initfn },
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{ .name = "pxa260", .initfn = pxa260_initfn },
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{ .name = "pxa261", .initfn = pxa261_initfn },
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{ .name = "pxa262", .initfn = pxa262_initfn },
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/* "pxa270" is an alias for "pxa270-a0" */
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{ .name = "pxa270", .initfn = pxa270a0_initfn },
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{ .name = "pxa270-a0", .initfn = pxa270a0_initfn },
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{ .name = "pxa270-a1", .initfn = pxa270a1_initfn },
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{ .name = "pxa270-b0", .initfn = pxa270b0_initfn },
|
|
{ .name = "pxa270-b1", .initfn = pxa270b1_initfn },
|
|
{ .name = "pxa270-c0", .initfn = pxa270c0_initfn },
|
|
{ .name = "pxa270-c5", .initfn = pxa270c5_initfn },
|
|
{ .name = "any", .initfn = arm_any_initfn },
|
|
};
|
|
|
|
static void arm_cpu_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
ARMCPUClass *acc = ARM_CPU_CLASS(oc);
|
|
CPUClass *cc = CPU_CLASS(acc);
|
|
|
|
acc->parent_reset = cc->reset;
|
|
cc->reset = arm_cpu_reset;
|
|
}
|
|
|
|
static void cpu_register(const ARMCPUInfo *info)
|
|
{
|
|
TypeInfo type_info = {
|
|
.name = info->name,
|
|
.parent = TYPE_ARM_CPU,
|
|
.instance_size = sizeof(ARMCPU),
|
|
.instance_init = info->initfn,
|
|
.class_size = sizeof(ARMCPUClass),
|
|
};
|
|
|
|
type_register_static(&type_info);
|
|
}
|
|
|
|
static const TypeInfo arm_cpu_type_info = {
|
|
.name = TYPE_ARM_CPU,
|
|
.parent = TYPE_CPU,
|
|
.instance_size = sizeof(ARMCPU),
|
|
.instance_init = arm_cpu_initfn,
|
|
.abstract = true,
|
|
.class_size = sizeof(ARMCPUClass),
|
|
.class_init = arm_cpu_class_init,
|
|
};
|
|
|
|
static void arm_cpu_register_types(void)
|
|
{
|
|
int i;
|
|
|
|
type_register_static(&arm_cpu_type_info);
|
|
for (i = 0; i < ARRAY_SIZE(arm_cpus); i++) {
|
|
cpu_register(&arm_cpus[i]);
|
|
}
|
|
}
|
|
|
|
type_init(arm_cpu_register_types)
|