To ease maintenance, move all TCG specific files under the tcg/ sub-directory. Adapt the Meson machinery. The following prototypes: - mips_tcg_init() - mips_cpu_do_unaligned_access() - mips_cpu_do_transaction_failed() can now be restricted to the "tcg-internal.h" header. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-29-f4bug@amsat.org>
168 lines
4.9 KiB
C
168 lines
4.9 KiB
C
/*
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* MIPS Exceptions processing helpers for QEMU.
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*
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* Copyright (c) 2004-2005 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "internal.h"
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#include "exec/helper-proto.h"
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#include "exec/exec-all.h"
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target_ulong exception_resume_pc(CPUMIPSState *env)
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{
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target_ulong bad_pc;
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target_ulong isa_mode;
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isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
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bad_pc = env->active_tc.PC | isa_mode;
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if (env->hflags & MIPS_HFLAG_BMASK) {
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/*
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* If the exception was raised from a delay slot, come back to
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* the jump.
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*/
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bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
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}
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return bad_pc;
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}
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void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
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int error_code)
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{
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do_raise_exception_err(env, exception, error_code, 0);
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}
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void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
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{
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do_raise_exception(env, exception, GETPC());
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}
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void helper_raise_exception_debug(CPUMIPSState *env)
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{
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do_raise_exception(env, EXCP_DEBUG, 0);
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}
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static void raise_exception(CPUMIPSState *env, uint32_t exception)
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{
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do_raise_exception(env, exception, 0);
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}
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void helper_wait(CPUMIPSState *env)
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{
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CPUState *cs = env_cpu(env);
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cs->halted = 1;
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cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
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/*
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* Last instruction in the block, PC was updated before
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* - no need to recover PC and icount.
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*/
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raise_exception(env, EXCP_HLT);
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}
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void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb)
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{
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MIPSCPU *cpu = MIPS_CPU(cs);
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CPUMIPSState *env = &cpu->env;
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env->active_tc.PC = tb->pc;
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env->hflags &= ~MIPS_HFLAG_BMASK;
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env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
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}
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bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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{
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if (interrupt_request & CPU_INTERRUPT_HARD) {
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MIPSCPU *cpu = MIPS_CPU(cs);
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CPUMIPSState *env = &cpu->env;
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if (cpu_mips_hw_interrupts_enabled(env) &&
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cpu_mips_hw_interrupts_pending(env)) {
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/* Raise it */
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cs->exception_index = EXCP_EXT_INTERRUPT;
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env->error_code = 0;
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mips_cpu_do_interrupt(cs);
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return true;
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}
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}
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return false;
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}
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static const char * const excp_names[EXCP_LAST + 1] = {
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[EXCP_RESET] = "reset",
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[EXCP_SRESET] = "soft reset",
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[EXCP_DSS] = "debug single step",
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[EXCP_DINT] = "debug interrupt",
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[EXCP_NMI] = "non-maskable interrupt",
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[EXCP_MCHECK] = "machine check",
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[EXCP_EXT_INTERRUPT] = "interrupt",
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[EXCP_DFWATCH] = "deferred watchpoint",
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[EXCP_DIB] = "debug instruction breakpoint",
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[EXCP_IWATCH] = "instruction fetch watchpoint",
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[EXCP_AdEL] = "address error load",
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[EXCP_AdES] = "address error store",
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[EXCP_TLBF] = "TLB refill",
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[EXCP_IBE] = "instruction bus error",
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[EXCP_DBp] = "debug breakpoint",
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[EXCP_SYSCALL] = "syscall",
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[EXCP_BREAK] = "break",
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[EXCP_CpU] = "coprocessor unusable",
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[EXCP_RI] = "reserved instruction",
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[EXCP_OVERFLOW] = "arithmetic overflow",
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[EXCP_TRAP] = "trap",
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[EXCP_FPE] = "floating point",
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[EXCP_DDBS] = "debug data break store",
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[EXCP_DWATCH] = "data watchpoint",
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[EXCP_LTLBL] = "TLB modify",
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[EXCP_TLBL] = "TLB load",
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[EXCP_TLBS] = "TLB store",
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[EXCP_DBE] = "data bus error",
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[EXCP_DDBL] = "debug data break load",
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[EXCP_THREAD] = "thread",
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[EXCP_MDMX] = "MDMX",
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[EXCP_C2E] = "precise coprocessor 2",
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[EXCP_CACHE] = "cache error",
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[EXCP_TLBXI] = "TLB execute-inhibit",
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[EXCP_TLBRI] = "TLB read-inhibit",
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[EXCP_MSADIS] = "MSA disabled",
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[EXCP_MSAFPE] = "MSA floating point",
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};
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const char *mips_exception_name(int32_t exception)
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{
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if (exception < 0 || exception > EXCP_LAST) {
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return "unknown";
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}
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return excp_names[exception];
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}
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void do_raise_exception_err(CPUMIPSState *env, uint32_t exception,
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int error_code, uintptr_t pc)
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{
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CPUState *cs = env_cpu(env);
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qemu_log_mask(CPU_LOG_INT, "%s: %d (%s) %d\n",
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__func__, exception, mips_exception_name(exception),
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error_code);
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cs->exception_index = exception;
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env->error_code = error_code;
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cpu_loop_exit_restore(cs, pc);
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}
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