changes generated using the following Coccinelle patch: @@ type DeviceParentClass; DeviceParentClass *pc; DeviceClass *dc; identifier parent_fn; identifier child_fn; @@ ( +device_class_set_parent_realize(dc, child_fn, &pc->parent_fn); -pc->parent_fn = dc->realize; ... -dc->realize = child_fn; | +device_class_set_parent_unrealize(dc, child_fn, &pc->parent_fn); -pc->parent_fn = dc->unrealize; ... -dc->unrealize = child_fn; | +device_class_set_parent_reset(dc, child_fn, &pc->parent_fn); -pc->parent_fn = dc->reset; ... -dc->reset = child_fn; ) Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180114020412.26160-4-f4bug@amsat.org> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Acked-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
317 lines
8.6 KiB
C
317 lines
8.6 KiB
C
/*
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* QEMU CRIS CPU
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*
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* Copyright (c) 2008 AXIS Communications AB
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* Written by Edgar E. Iglesias.
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*
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "qemu-common.h"
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#include "mmu.h"
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#include "exec/exec-all.h"
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static void cris_cpu_set_pc(CPUState *cs, vaddr value)
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{
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CRISCPU *cpu = CRIS_CPU(cs);
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cpu->env.pc = value;
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}
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static bool cris_cpu_has_work(CPUState *cs)
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{
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return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
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}
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/* CPUClass::reset() */
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static void cris_cpu_reset(CPUState *s)
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{
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CRISCPU *cpu = CRIS_CPU(s);
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CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(cpu);
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CPUCRISState *env = &cpu->env;
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uint32_t vr;
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ccc->parent_reset(s);
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vr = env->pregs[PR_VR];
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memset(env, 0, offsetof(CPUCRISState, end_reset_fields));
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env->pregs[PR_VR] = vr;
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#if defined(CONFIG_USER_ONLY)
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/* start in user mode with interrupts enabled. */
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env->pregs[PR_CCS] |= U_FLAG | I_FLAG | P_FLAG;
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#else
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cris_mmu_init(env);
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env->pregs[PR_CCS] = 0;
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#endif
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}
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static ObjectClass *cris_cpu_class_by_name(const char *cpu_model)
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{
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ObjectClass *oc;
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char *typename;
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#if defined(CONFIG_USER_ONLY)
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if (strcasecmp(cpu_model, "any") == 0) {
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return object_class_by_name(CRIS_CPU_TYPE_NAME("crisv32"));
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}
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#endif
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typename = g_strdup_printf(CRIS_CPU_TYPE_NAME("%s"), cpu_model);
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oc = object_class_by_name(typename);
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g_free(typename);
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if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_CRIS_CPU) ||
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object_class_is_abstract(oc))) {
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oc = NULL;
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}
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return oc;
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}
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/* Sort alphabetically by VR. */
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static gint cris_cpu_list_compare(gconstpointer a, gconstpointer b)
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{
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CRISCPUClass *ccc_a = CRIS_CPU_CLASS(a);
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CRISCPUClass *ccc_b = CRIS_CPU_CLASS(b);
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/* */
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if (ccc_a->vr > ccc_b->vr) {
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return 1;
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} else if (ccc_a->vr < ccc_b->vr) {
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return -1;
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} else {
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return 0;
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}
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}
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static void cris_cpu_list_entry(gpointer data, gpointer user_data)
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{
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ObjectClass *oc = data;
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CPUListState *s = user_data;
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const char *typename = object_class_get_name(oc);
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char *name;
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name = g_strndup(typename, strlen(typename) - strlen(CRIS_CPU_TYPE_SUFFIX));
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(*s->cpu_fprintf)(s->file, " %s\n", name);
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g_free(name);
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}
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void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf)
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{
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CPUListState s = {
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.file = f,
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.cpu_fprintf = cpu_fprintf,
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};
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GSList *list;
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list = object_class_get_list(TYPE_CRIS_CPU, false);
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list = g_slist_sort(list, cris_cpu_list_compare);
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(*cpu_fprintf)(f, "Available CPUs:\n");
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g_slist_foreach(list, cris_cpu_list_entry, &s);
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g_slist_free(list);
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}
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static void cris_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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CPUState *cs = CPU(dev);
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CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(dev);
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Error *local_err = NULL;
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cpu_exec_realizefn(cs, &local_err);
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if (local_err != NULL) {
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error_propagate(errp, local_err);
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return;
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}
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cpu_reset(cs);
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qemu_init_vcpu(cs);
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ccc->parent_realize(dev, errp);
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}
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#ifndef CONFIG_USER_ONLY
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static void cris_cpu_set_irq(void *opaque, int irq, int level)
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{
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CRISCPU *cpu = opaque;
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CPUState *cs = CPU(cpu);
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int type = irq == CRIS_CPU_IRQ ? CPU_INTERRUPT_HARD : CPU_INTERRUPT_NMI;
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if (level) {
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cpu_interrupt(cs, type);
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} else {
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cpu_reset_interrupt(cs, type);
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}
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}
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#endif
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static void cris_disas_set_info(CPUState *cpu, disassemble_info *info)
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{
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CRISCPU *cc = CRIS_CPU(cpu);
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CPUCRISState *env = &cc->env;
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if (env->pregs[PR_VR] != 32) {
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info->mach = bfd_mach_cris_v0_v10;
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info->print_insn = print_insn_crisv10;
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} else {
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info->mach = bfd_mach_cris_v32;
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info->print_insn = print_insn_crisv32;
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}
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}
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static void cris_cpu_initfn(Object *obj)
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{
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CPUState *cs = CPU(obj);
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CRISCPU *cpu = CRIS_CPU(obj);
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CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(obj);
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CPUCRISState *env = &cpu->env;
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cs->env_ptr = env;
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env->pregs[PR_VR] = ccc->vr;
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#ifndef CONFIG_USER_ONLY
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/* IRQ and NMI lines. */
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qdev_init_gpio_in(DEVICE(cpu), cris_cpu_set_irq, 2);
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#endif
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}
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static void crisv8_cpu_class_init(ObjectClass *oc, void *data)
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{
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CPUClass *cc = CPU_CLASS(oc);
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CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
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ccc->vr = 8;
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cc->do_interrupt = crisv10_cpu_do_interrupt;
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cc->gdb_read_register = crisv10_cpu_gdb_read_register;
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cc->tcg_initialize = cris_initialize_crisv10_tcg;
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}
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static void crisv9_cpu_class_init(ObjectClass *oc, void *data)
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{
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CPUClass *cc = CPU_CLASS(oc);
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CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
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ccc->vr = 9;
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cc->do_interrupt = crisv10_cpu_do_interrupt;
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cc->gdb_read_register = crisv10_cpu_gdb_read_register;
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cc->tcg_initialize = cris_initialize_crisv10_tcg;
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}
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static void crisv10_cpu_class_init(ObjectClass *oc, void *data)
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{
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CPUClass *cc = CPU_CLASS(oc);
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CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
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ccc->vr = 10;
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cc->do_interrupt = crisv10_cpu_do_interrupt;
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cc->gdb_read_register = crisv10_cpu_gdb_read_register;
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cc->tcg_initialize = cris_initialize_crisv10_tcg;
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}
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static void crisv11_cpu_class_init(ObjectClass *oc, void *data)
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{
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CPUClass *cc = CPU_CLASS(oc);
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CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
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ccc->vr = 11;
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cc->do_interrupt = crisv10_cpu_do_interrupt;
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cc->gdb_read_register = crisv10_cpu_gdb_read_register;
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cc->tcg_initialize = cris_initialize_crisv10_tcg;
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}
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static void crisv17_cpu_class_init(ObjectClass *oc, void *data)
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{
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CPUClass *cc = CPU_CLASS(oc);
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CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
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ccc->vr = 17;
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cc->do_interrupt = crisv10_cpu_do_interrupt;
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cc->gdb_read_register = crisv10_cpu_gdb_read_register;
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cc->tcg_initialize = cris_initialize_crisv10_tcg;
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}
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static void crisv32_cpu_class_init(ObjectClass *oc, void *data)
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{
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CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
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ccc->vr = 32;
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}
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static void cris_cpu_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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CPUClass *cc = CPU_CLASS(oc);
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CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
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device_class_set_parent_realize(dc, cris_cpu_realizefn,
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&ccc->parent_realize);
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ccc->parent_reset = cc->reset;
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cc->reset = cris_cpu_reset;
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cc->class_by_name = cris_cpu_class_by_name;
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cc->has_work = cris_cpu_has_work;
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cc->do_interrupt = cris_cpu_do_interrupt;
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cc->cpu_exec_interrupt = cris_cpu_exec_interrupt;
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cc->dump_state = cris_cpu_dump_state;
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cc->set_pc = cris_cpu_set_pc;
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cc->gdb_read_register = cris_cpu_gdb_read_register;
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cc->gdb_write_register = cris_cpu_gdb_write_register;
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#ifdef CONFIG_USER_ONLY
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cc->handle_mmu_fault = cris_cpu_handle_mmu_fault;
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#else
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cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
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dc->vmsd = &vmstate_cris_cpu;
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#endif
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cc->gdb_num_core_regs = 49;
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cc->gdb_stop_before_watchpoint = true;
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cc->disas_set_info = cris_disas_set_info;
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cc->tcg_initialize = cris_initialize_tcg;
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}
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#define DEFINE_CRIS_CPU_TYPE(cpu_model, initfn) \
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{ \
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.parent = TYPE_CRIS_CPU, \
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.class_init = initfn, \
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.name = CRIS_CPU_TYPE_NAME(cpu_model), \
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}
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static const TypeInfo cris_cpu_model_type_infos[] = {
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{
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.name = TYPE_CRIS_CPU,
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.parent = TYPE_CPU,
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.instance_size = sizeof(CRISCPU),
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.instance_init = cris_cpu_initfn,
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.abstract = true,
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.class_size = sizeof(CRISCPUClass),
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.class_init = cris_cpu_class_init,
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},
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DEFINE_CRIS_CPU_TYPE("crisv8", crisv8_cpu_class_init),
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DEFINE_CRIS_CPU_TYPE("crisv9", crisv9_cpu_class_init),
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DEFINE_CRIS_CPU_TYPE("crisv10", crisv10_cpu_class_init),
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DEFINE_CRIS_CPU_TYPE("crisv11", crisv11_cpu_class_init),
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DEFINE_CRIS_CPU_TYPE("crisv17", crisv17_cpu_class_init),
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DEFINE_CRIS_CPU_TYPE("crisv32", crisv32_cpu_class_init),
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};
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DEFINE_TYPES(cris_cpu_model_type_infos)
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