Add the subset of the libvixl sources that are needed for the A64 disassembler support. These sources come from https://github.com/armvixl/vixl commit 578645f14e122d2b which is VIXL release 1.1. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
239 lines
7.4 KiB
C++
239 lines
7.4 KiB
C++
// Copyright 2013, ARM Limited
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// * Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// * Neither the name of ARM Limited nor the names of its contributors may be
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// used to endorse or promote products derived from this software without
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// specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
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// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#include "a64/instructions-a64.h"
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#include "a64/assembler-a64.h"
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namespace vixl {
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static uint64_t RotateRight(uint64_t value,
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unsigned int rotate,
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unsigned int width) {
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ASSERT(width <= 64);
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rotate &= 63;
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return ((value & ((1UL << rotate) - 1UL)) << (width - rotate)) |
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(value >> rotate);
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}
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static uint64_t RepeatBitsAcrossReg(unsigned reg_size,
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uint64_t value,
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unsigned width) {
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ASSERT((width == 2) || (width == 4) || (width == 8) || (width == 16) ||
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(width == 32));
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ASSERT((reg_size == kWRegSize) || (reg_size == kXRegSize));
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uint64_t result = value & ((1UL << width) - 1UL);
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for (unsigned i = width; i < reg_size; i *= 2) {
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result |= (result << i);
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}
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return result;
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}
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// Logical immediates can't encode zero, so a return value of zero is used to
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// indicate a failure case. Specifically, where the constraints on imm_s are
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// not met.
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uint64_t Instruction::ImmLogical() {
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unsigned reg_size = SixtyFourBits() ? kXRegSize : kWRegSize;
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int64_t n = BitN();
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int64_t imm_s = ImmSetBits();
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int64_t imm_r = ImmRotate();
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// An integer is constructed from the n, imm_s and imm_r bits according to
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// the following table:
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//
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// N imms immr size S R
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// 1 ssssss rrrrrr 64 UInt(ssssss) UInt(rrrrrr)
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// 0 0sssss xrrrrr 32 UInt(sssss) UInt(rrrrr)
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// 0 10ssss xxrrrr 16 UInt(ssss) UInt(rrrr)
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// 0 110sss xxxrrr 8 UInt(sss) UInt(rrr)
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// 0 1110ss xxxxrr 4 UInt(ss) UInt(rr)
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// 0 11110s xxxxxr 2 UInt(s) UInt(r)
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// (s bits must not be all set)
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//
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// A pattern is constructed of size bits, where the least significant S+1
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// bits are set. The pattern is rotated right by R, and repeated across a
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// 32 or 64-bit value, depending on destination register width.
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//
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if (n == 1) {
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if (imm_s == 0x3F) {
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return 0;
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}
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uint64_t bits = (1UL << (imm_s + 1)) - 1;
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return RotateRight(bits, imm_r, 64);
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} else {
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if ((imm_s >> 1) == 0x1F) {
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return 0;
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}
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for (int width = 0x20; width >= 0x2; width >>= 1) {
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if ((imm_s & width) == 0) {
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int mask = width - 1;
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if ((imm_s & mask) == mask) {
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return 0;
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}
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uint64_t bits = (1UL << ((imm_s & mask) + 1)) - 1;
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return RepeatBitsAcrossReg(reg_size,
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RotateRight(bits, imm_r & mask, width),
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width);
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}
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}
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}
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UNREACHABLE();
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return 0;
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}
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float Instruction::ImmFP32() {
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// ImmFP: abcdefgh (8 bits)
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// Single: aBbb.bbbc.defg.h000.0000.0000.0000.0000 (32 bits)
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// where B is b ^ 1
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uint32_t bits = ImmFP();
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uint32_t bit7 = (bits >> 7) & 0x1;
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uint32_t bit6 = (bits >> 6) & 0x1;
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uint32_t bit5_to_0 = bits & 0x3f;
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uint32_t result = (bit7 << 31) | ((32 - bit6) << 25) | (bit5_to_0 << 19);
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return rawbits_to_float(result);
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}
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double Instruction::ImmFP64() {
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// ImmFP: abcdefgh (8 bits)
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// Double: aBbb.bbbb.bbcd.efgh.0000.0000.0000.0000
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// 0000.0000.0000.0000.0000.0000.0000.0000 (64 bits)
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// where B is b ^ 1
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uint32_t bits = ImmFP();
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uint64_t bit7 = (bits >> 7) & 0x1;
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uint64_t bit6 = (bits >> 6) & 0x1;
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uint64_t bit5_to_0 = bits & 0x3f;
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uint64_t result = (bit7 << 63) | ((256 - bit6) << 54) | (bit5_to_0 << 48);
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return rawbits_to_double(result);
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}
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LSDataSize CalcLSPairDataSize(LoadStorePairOp op) {
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switch (op) {
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case STP_x:
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case LDP_x:
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case STP_d:
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case LDP_d: return LSDoubleWord;
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default: return LSWord;
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}
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}
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Instruction* Instruction::ImmPCOffsetTarget() {
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ptrdiff_t offset;
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if (IsPCRelAddressing()) {
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// PC-relative addressing. Only ADR is supported.
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offset = ImmPCRel();
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} else {
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// All PC-relative branches.
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ASSERT(BranchType() != UnknownBranchType);
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// Relative branch offsets are instruction-size-aligned.
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offset = ImmBranch() << kInstructionSizeLog2;
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}
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return this + offset;
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}
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inline int Instruction::ImmBranch() const {
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switch (BranchType()) {
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case CondBranchType: return ImmCondBranch();
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case UncondBranchType: return ImmUncondBranch();
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case CompareBranchType: return ImmCmpBranch();
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case TestBranchType: return ImmTestBranch();
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default: UNREACHABLE();
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}
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return 0;
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}
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void Instruction::SetImmPCOffsetTarget(Instruction* target) {
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if (IsPCRelAddressing()) {
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SetPCRelImmTarget(target);
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} else {
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SetBranchImmTarget(target);
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}
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}
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void Instruction::SetPCRelImmTarget(Instruction* target) {
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// ADRP is not supported, so 'this' must point to an ADR instruction.
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ASSERT(Mask(PCRelAddressingMask) == ADR);
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Instr imm = Assembler::ImmPCRelAddress(target - this);
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SetInstructionBits(Mask(~ImmPCRel_mask) | imm);
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}
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void Instruction::SetBranchImmTarget(Instruction* target) {
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ASSERT(((target - this) & 3) == 0);
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Instr branch_imm = 0;
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uint32_t imm_mask = 0;
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int offset = (target - this) >> kInstructionSizeLog2;
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switch (BranchType()) {
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case CondBranchType: {
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branch_imm = Assembler::ImmCondBranch(offset);
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imm_mask = ImmCondBranch_mask;
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break;
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}
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case UncondBranchType: {
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branch_imm = Assembler::ImmUncondBranch(offset);
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imm_mask = ImmUncondBranch_mask;
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break;
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}
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case CompareBranchType: {
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branch_imm = Assembler::ImmCmpBranch(offset);
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imm_mask = ImmCmpBranch_mask;
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break;
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}
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case TestBranchType: {
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branch_imm = Assembler::ImmTestBranch(offset);
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imm_mask = ImmTestBranch_mask;
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break;
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}
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default: UNREACHABLE();
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}
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SetInstructionBits(Mask(~imm_mask) | branch_imm);
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}
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void Instruction::SetImmLLiteral(Instruction* source) {
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ASSERT(((source - this) & 3) == 0);
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int offset = (source - this) >> kLiteralEntrySizeLog2;
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Instr imm = Assembler::ImmLLiteral(offset);
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Instr mask = ImmLLiteral_mask;
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SetInstructionBits(Mask(~mask) | imm);
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}
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} // namespace vixl
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