In preparation for having some more common semihosting code let's excise the current config magic from vl.c into its own file. We shall later add more conditionals to the build configurations so we can avoid building this if we don't need it. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
233 lines
6.5 KiB
C
233 lines
6.5 KiB
C
/*
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* LatticeMico32 helper routines.
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*
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* Copyright (c) 2010-2014 Michael Walle <michael@walle.cc>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "qemu/host-utils.h"
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#include "sysemu/sysemu.h"
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#include "hw/semihosting/semihost.h"
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#include "exec/log.h"
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bool lm32_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr)
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{
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LM32CPU *cpu = LM32_CPU(cs);
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CPULM32State *env = &cpu->env;
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int prot;
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address &= TARGET_PAGE_MASK;
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prot = PAGE_BITS;
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if (env->flags & LM32_FLAG_IGNORE_MSB) {
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tlb_set_page(cs, address, address & 0x7fffffff, prot, mmu_idx,
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TARGET_PAGE_SIZE);
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} else {
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tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
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}
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return true;
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}
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hwaddr lm32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
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{
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LM32CPU *cpu = LM32_CPU(cs);
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addr &= TARGET_PAGE_MASK;
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if (cpu->env.flags & LM32_FLAG_IGNORE_MSB) {
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return addr & 0x7fffffff;
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} else {
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return addr;
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}
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}
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void lm32_breakpoint_insert(CPULM32State *env, int idx, target_ulong address)
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{
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LM32CPU *cpu = lm32_env_get_cpu(env);
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cpu_breakpoint_insert(CPU(cpu), address, BP_CPU,
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&env->cpu_breakpoint[idx]);
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}
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void lm32_breakpoint_remove(CPULM32State *env, int idx)
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{
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LM32CPU *cpu = lm32_env_get_cpu(env);
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if (!env->cpu_breakpoint[idx]) {
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return;
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}
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cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[idx]);
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env->cpu_breakpoint[idx] = NULL;
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}
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void lm32_watchpoint_insert(CPULM32State *env, int idx, target_ulong address,
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lm32_wp_t wp_type)
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{
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LM32CPU *cpu = lm32_env_get_cpu(env);
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int flags = 0;
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switch (wp_type) {
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case LM32_WP_DISABLED:
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/* nothing to do */
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break;
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case LM32_WP_READ:
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flags = BP_CPU | BP_STOP_BEFORE_ACCESS | BP_MEM_READ;
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break;
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case LM32_WP_WRITE:
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flags = BP_CPU | BP_STOP_BEFORE_ACCESS | BP_MEM_WRITE;
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break;
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case LM32_WP_READ_WRITE:
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flags = BP_CPU | BP_STOP_BEFORE_ACCESS | BP_MEM_ACCESS;
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break;
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}
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if (flags != 0) {
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cpu_watchpoint_insert(CPU(cpu), address, 1, flags,
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&env->cpu_watchpoint[idx]);
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}
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}
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void lm32_watchpoint_remove(CPULM32State *env, int idx)
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{
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LM32CPU *cpu = lm32_env_get_cpu(env);
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if (!env->cpu_watchpoint[idx]) {
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return;
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}
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cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[idx]);
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env->cpu_watchpoint[idx] = NULL;
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}
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static bool check_watchpoints(CPULM32State *env)
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{
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LM32CPU *cpu = lm32_env_get_cpu(env);
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int i;
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for (i = 0; i < cpu->num_watchpoints; i++) {
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if (env->cpu_watchpoint[i] &&
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env->cpu_watchpoint[i]->flags & BP_WATCHPOINT_HIT) {
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return true;
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}
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}
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return false;
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}
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void lm32_debug_excp_handler(CPUState *cs)
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{
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LM32CPU *cpu = LM32_CPU(cs);
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CPULM32State *env = &cpu->env;
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CPUBreakpoint *bp;
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if (cs->watchpoint_hit) {
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if (cs->watchpoint_hit->flags & BP_CPU) {
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cs->watchpoint_hit = NULL;
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if (check_watchpoints(env)) {
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raise_exception(env, EXCP_WATCHPOINT);
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} else {
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cpu_loop_exit_noexc(cs);
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}
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}
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} else {
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QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
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if (bp->pc == env->pc) {
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if (bp->flags & BP_CPU) {
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raise_exception(env, EXCP_BREAKPOINT);
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}
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break;
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}
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}
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}
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}
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void lm32_cpu_do_interrupt(CPUState *cs)
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{
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LM32CPU *cpu = LM32_CPU(cs);
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CPULM32State *env = &cpu->env;
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qemu_log_mask(CPU_LOG_INT,
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"exception at pc=%x type=%x\n", env->pc, cs->exception_index);
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switch (cs->exception_index) {
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case EXCP_SYSTEMCALL:
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if (unlikely(semihosting_enabled())) {
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/* do_semicall() returns true if call was handled. Otherwise
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* do the normal exception handling. */
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if (lm32_cpu_do_semihosting(cs)) {
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env->pc += 4;
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break;
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}
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}
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/* fall through */
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case EXCP_INSN_BUS_ERROR:
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case EXCP_DATA_BUS_ERROR:
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case EXCP_DIVIDE_BY_ZERO:
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case EXCP_IRQ:
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/* non-debug exceptions */
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env->regs[R_EA] = env->pc;
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env->ie |= (env->ie & IE_IE) ? IE_EIE : 0;
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env->ie &= ~IE_IE;
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if (env->dc & DC_RE) {
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env->pc = env->deba + (cs->exception_index * 32);
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} else {
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env->pc = env->eba + (cs->exception_index * 32);
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}
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log_cpu_state_mask(CPU_LOG_INT, cs, 0);
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break;
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case EXCP_BREAKPOINT:
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case EXCP_WATCHPOINT:
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/* debug exceptions */
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env->regs[R_BA] = env->pc;
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env->ie |= (env->ie & IE_IE) ? IE_BIE : 0;
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env->ie &= ~IE_IE;
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env->pc = env->deba + (cs->exception_index * 32);
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log_cpu_state_mask(CPU_LOG_INT, cs, 0);
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break;
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default:
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cpu_abort(cs, "unhandled exception type=%d\n",
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cs->exception_index);
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break;
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}
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}
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bool lm32_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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{
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LM32CPU *cpu = LM32_CPU(cs);
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CPULM32State *env = &cpu->env;
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if ((interrupt_request & CPU_INTERRUPT_HARD) && (env->ie & IE_IE)) {
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cs->exception_index = EXCP_IRQ;
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lm32_cpu_do_interrupt(cs);
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return true;
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}
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return false;
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}
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/* Some soc ignores the MSB on the address bus. Thus creating a shadow memory
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* area. As a general rule, 0x00000000-0x7fffffff is cached, whereas
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* 0x80000000-0xffffffff is not cached and used to access IO devices. */
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void cpu_lm32_set_phys_msb_ignore(CPULM32State *env, int value)
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{
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if (value) {
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env->flags |= LM32_FLAG_IGNORE_MSB;
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} else {
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env->flags &= ~LM32_FLAG_IGNORE_MSB;
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}
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}
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