Reorganize special register handling to support configurations with conflicting SR definitions. Implement options used by the modern xtensa cores: - memory protection unit; - block prefetch; - exclusive access Add special register definitions and IRQ types for ECC/parity, gather/scatter and IDMA. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEK2eFS5jlMn3N6xfYUfnMkfg/oEQFAlzi6YETHGpjbXZia2Jj QGdtYWlsLmNvbQAKCRBR+cyR+D+gRNOfD/96OTPguHCDvYtOXqcQ9MpDdbGiMU/U 9UMUietClexHgSIO6mYh4ZF1lApn9UqCqynktNUNQ1HeWhLjc9kka9X9wDSG5VJP kxF4Wt6S6+Re1DBw6KsuHwJTkcrxHnxMDVHEhedjM13bWtnGj0B9SOzGwhN2PVYi +52OWRa/kMa+1M79BG7f49JujFRpDLGRogivrr45XC+kDsP/tSprhZvIO8lF7xpZ MW3i6FdOXQEZKJrVojpQkUU5rm18JojdOBcCY2qvCLpaWfUNW+wNuh1aqT/teUAq ZPOT0NIaq9uBwZ5DNRZxAGVB0MVASYWwMgYoLMcXo8XJdvHUnf9waAs+J4Dl6nfG aiYIWCXENkZ9MDAd672HVb+/gdXp8FDYoazM2+CE4LgPKuGqM+bunVE8OJ/F3rGL iftqx/sb/N09tXFsqINFSaxnkc7kZ1ikQRnonD4CHidcEzyUjJ1X98PAl/vm97yA jpS4OMZXUfNYm5HaGNiDPimhychw2lnHoNUNdlrZ1i6IX5VqSAs8LqDBd3B6ouIr /UKmRyXCgvbU90KC5wdPpPFKvb76SEvfzA+dmGjuP4bhKQvNwcG+zyHpdBaIa4pR 2wrPCICE/07UP5nFLB90SFdfGS/XEJY9RjbGoUY/AOpfdrsASR4QGavI5pmiy71y nK9T0qe/2necVQ== =5Vz/ -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/xtensa/tags/20190520-xtensa' into staging target/xtensa: SR reorganization and options for modern cores Reorganize special register handling to support configurations with conflicting SR definitions. Implement options used by the modern xtensa cores: - memory protection unit; - block prefetch; - exclusive access Add special register definitions and IRQ types for ECC/parity, gather/scatter and IDMA. # gpg: Signature made Mon 20 May 2019 18:53:05 BST # gpg: using RSA key 2B67854B98E5327DCDEB17D851F9CC91F83FA044 # gpg: issuer "jcmvbkbc@gmail.com" # gpg: Good signature from "Max Filippov <filippov@cadence.com>" [unknown] # gpg: aka "Max Filippov <max.filippov@cogentembedded.com>" [full] # gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" [full] # Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044 * remotes/xtensa/tags/20190520-xtensa: target/xtensa: implement exclusive access option target/xtensa: update list of exception causes target/xtensa: implement block prefetch option opcodes target/xtensa: implement DIWBUI.P opcode target/xtensa: implement MPU option target/xtensa: add parity/ECC option SRs target/xtensa: define IDMA and gather/scatter IRQ types target/xtensa: make internal MMU functions static target/xtensa: get rid of centralized SR properties Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
338 lines
11 KiB
C
338 lines
11 KiB
C
/*
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* Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the Open Source and Linux Lab nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "exec/gdbstub.h"
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#include "exec/helper-proto.h"
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#include "qemu/error-report.h"
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#include "qemu/qemu-print.h"
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#include "qemu/host-utils.h"
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static struct XtensaConfigList *xtensa_cores;
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static void add_translator_to_hash(GHashTable *translator,
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const char *name,
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const XtensaOpcodeOps *opcode)
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{
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if (!g_hash_table_insert(translator, (void *)name, (void *)opcode)) {
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error_report("Multiple definitions of '%s' opcode in a single table",
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name);
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}
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}
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static GHashTable *hash_opcode_translators(const XtensaOpcodeTranslators *t)
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{
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unsigned i, j;
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GHashTable *translator = g_hash_table_new(g_str_hash, g_str_equal);
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for (i = 0; i < t->num_opcodes; ++i) {
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if (t->opcode[i].op_flags & XTENSA_OP_NAME_ARRAY) {
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const char * const *name = t->opcode[i].name;
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for (j = 0; name[j]; ++j) {
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add_translator_to_hash(translator,
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(void *)name[j],
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(void *)(t->opcode + i));
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}
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} else {
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add_translator_to_hash(translator,
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(void *)t->opcode[i].name,
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(void *)(t->opcode + i));
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}
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}
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return translator;
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}
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static XtensaOpcodeOps *
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xtensa_find_opcode_ops(const XtensaOpcodeTranslators *t,
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const char *name)
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{
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static GHashTable *translators;
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GHashTable *translator;
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if (translators == NULL) {
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translators = g_hash_table_new(g_direct_hash, g_direct_equal);
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}
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translator = g_hash_table_lookup(translators, t);
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if (translator == NULL) {
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translator = hash_opcode_translators(t);
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g_hash_table_insert(translators, (void *)t, translator);
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}
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return g_hash_table_lookup(translator, name);
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}
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static void init_libisa(XtensaConfig *config)
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{
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unsigned i, j;
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unsigned opcodes;
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unsigned formats;
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unsigned regfiles;
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config->isa = xtensa_isa_init(config->isa_internal, NULL, NULL);
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assert(xtensa_isa_maxlength(config->isa) <= MAX_INSN_LENGTH);
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opcodes = xtensa_isa_num_opcodes(config->isa);
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formats = xtensa_isa_num_formats(config->isa);
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regfiles = xtensa_isa_num_regfiles(config->isa);
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config->opcode_ops = g_new(XtensaOpcodeOps *, opcodes);
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for (i = 0; i < formats; ++i) {
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assert(xtensa_format_num_slots(config->isa, i) <= MAX_INSN_SLOTS);
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}
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for (i = 0; i < opcodes; ++i) {
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const char *opc_name = xtensa_opcode_name(config->isa, i);
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XtensaOpcodeOps *ops = NULL;
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assert(xtensa_opcode_num_operands(config->isa, i) <= MAX_OPCODE_ARGS);
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if (!config->opcode_translators) {
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ops = xtensa_find_opcode_ops(&xtensa_core_opcodes, opc_name);
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} else {
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for (j = 0; !ops && config->opcode_translators[j]; ++j) {
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ops = xtensa_find_opcode_ops(config->opcode_translators[j],
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opc_name);
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}
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}
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#ifdef DEBUG
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if (ops == NULL) {
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fprintf(stderr,
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"opcode translator not found for %s's opcode '%s'\n",
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config->name, opc_name);
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}
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#endif
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config->opcode_ops[i] = ops;
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}
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config->a_regfile = xtensa_regfile_lookup(config->isa, "AR");
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config->regfile = g_new(void **, regfiles);
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for (i = 0; i < regfiles; ++i) {
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const char *name = xtensa_regfile_name(config->isa, i);
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config->regfile[i] = xtensa_get_regfile_by_name(name);
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#ifdef DEBUG
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if (config->regfile[i] == NULL) {
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fprintf(stderr, "regfile '%s' not found for %s\n",
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name, config->name);
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}
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#endif
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}
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xtensa_collect_sr_names(config);
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}
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static void xtensa_finalize_config(XtensaConfig *config)
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{
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if (config->isa_internal) {
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init_libisa(config);
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}
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if (config->gdb_regmap.num_regs == 0 ||
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config->gdb_regmap.num_core_regs == 0) {
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unsigned n_regs = 0;
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unsigned n_core_regs = 0;
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xtensa_count_regs(config, &n_regs, &n_core_regs);
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if (config->gdb_regmap.num_regs == 0) {
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config->gdb_regmap.num_regs = n_regs;
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}
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if (config->gdb_regmap.num_core_regs == 0) {
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config->gdb_regmap.num_core_regs = n_core_regs;
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}
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}
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}
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static void xtensa_core_class_init(ObjectClass *oc, void *data)
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{
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CPUClass *cc = CPU_CLASS(oc);
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XtensaCPUClass *xcc = XTENSA_CPU_CLASS(oc);
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XtensaConfig *config = data;
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xtensa_finalize_config(config);
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xcc->config = config;
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/*
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* Use num_core_regs to see only non-privileged registers in an unmodified
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* gdb. Use num_regs to see all registers. gdb modification is required
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* for that: reset bit 0 in the 'flags' field of the registers definitions
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* in the gdb/xtensa-config.c inside gdb source tree or inside gdb overlay.
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*/
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cc->gdb_num_core_regs = config->gdb_regmap.num_regs;
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}
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void xtensa_register_core(XtensaConfigList *node)
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{
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TypeInfo type = {
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.parent = TYPE_XTENSA_CPU,
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.class_init = xtensa_core_class_init,
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.class_data = (void *)node->config,
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};
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node->next = xtensa_cores;
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xtensa_cores = node;
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type.name = g_strdup_printf(XTENSA_CPU_TYPE_NAME("%s"), node->config->name);
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type_register(&type);
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g_free((gpointer)type.name);
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}
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static uint32_t check_hw_breakpoints(CPUXtensaState *env)
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{
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unsigned i;
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for (i = 0; i < env->config->ndbreak; ++i) {
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if (env->cpu_watchpoint[i] &&
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env->cpu_watchpoint[i]->flags & BP_WATCHPOINT_HIT) {
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return DEBUGCAUSE_DB | (i << DEBUGCAUSE_DBNUM_SHIFT);
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}
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}
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return 0;
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}
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void xtensa_breakpoint_handler(CPUState *cs)
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{
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XtensaCPU *cpu = XTENSA_CPU(cs);
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CPUXtensaState *env = &cpu->env;
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if (cs->watchpoint_hit) {
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if (cs->watchpoint_hit->flags & BP_CPU) {
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uint32_t cause;
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cs->watchpoint_hit = NULL;
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cause = check_hw_breakpoints(env);
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if (cause) {
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debug_exception_env(env, cause);
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}
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cpu_loop_exit_noexc(cs);
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}
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}
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}
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void xtensa_cpu_list(void)
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{
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XtensaConfigList *core = xtensa_cores;
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qemu_printf("Available CPUs:\n");
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for (; core; core = core->next) {
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qemu_printf(" %s\n", core->config->name);
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}
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}
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#ifdef CONFIG_USER_ONLY
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bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr)
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{
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XtensaCPU *cpu = XTENSA_CPU(cs);
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CPUXtensaState *env = &cpu->env;
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qemu_log_mask(CPU_LOG_INT,
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"%s: rw = %d, address = 0x%08" VADDR_PRIx ", size = %d\n",
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__func__, access_type, address, size);
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env->sregs[EXCVADDR] = address;
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env->sregs[EXCCAUSE] = (access_type == MMU_DATA_STORE ?
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STORE_PROHIBITED_CAUSE : LOAD_PROHIBITED_CAUSE);
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cs->exception_index = EXC_USER;
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cpu_loop_exit_restore(cs, retaddr);
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}
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#else
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void xtensa_cpu_do_unaligned_access(CPUState *cs,
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vaddr addr, MMUAccessType access_type,
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int mmu_idx, uintptr_t retaddr)
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{
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XtensaCPU *cpu = XTENSA_CPU(cs);
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CPUXtensaState *env = &cpu->env;
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if (xtensa_option_enabled(env->config, XTENSA_OPTION_UNALIGNED_EXCEPTION) &&
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!xtensa_option_enabled(env->config, XTENSA_OPTION_HW_ALIGNMENT)) {
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cpu_restore_state(CPU(cpu), retaddr, true);
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HELPER(exception_cause_vaddr)(env,
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env->pc, LOAD_STORE_ALIGNMENT_CAUSE,
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addr);
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}
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}
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bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr)
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{
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XtensaCPU *cpu = XTENSA_CPU(cs);
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CPUXtensaState *env = &cpu->env;
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uint32_t paddr;
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uint32_t page_size;
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unsigned access;
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int ret = xtensa_get_physical_addr(env, true, address, access_type,
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mmu_idx, &paddr, &page_size, &access);
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qemu_log_mask(CPU_LOG_MMU, "%s(%08" VADDR_PRIx
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", %d, %d) -> %08x, ret = %d\n",
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__func__, address, access_type, mmu_idx, paddr, ret);
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if (ret == 0) {
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tlb_set_page(cs,
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address & TARGET_PAGE_MASK,
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paddr & TARGET_PAGE_MASK,
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access, mmu_idx, page_size);
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return true;
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} else if (probe) {
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return false;
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} else {
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cpu_restore_state(cs, retaddr, true);
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HELPER(exception_cause_vaddr)(env, env->pc, ret, address);
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}
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}
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void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
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unsigned size, MMUAccessType access_type,
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int mmu_idx, MemTxAttrs attrs,
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MemTxResult response, uintptr_t retaddr)
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{
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XtensaCPU *cpu = XTENSA_CPU(cs);
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CPUXtensaState *env = &cpu->env;
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cpu_restore_state(cs, retaddr, true);
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HELPER(exception_cause_vaddr)(env, env->pc,
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access_type == MMU_INST_FETCH ?
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INSTR_PIF_ADDR_ERROR_CAUSE :
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LOAD_STORE_PIF_ADDR_ERROR_CAUSE,
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addr);
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}
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void xtensa_runstall(CPUXtensaState *env, bool runstall)
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{
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CPUState *cpu = CPU(xtensa_env_get_cpu(env));
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env->runstall = runstall;
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cpu->halted = runstall;
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if (runstall) {
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cpu_interrupt(cpu, CPU_INTERRUPT_HALT);
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} else {
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qemu_cpu_kick(cpu);
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}
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}
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#endif
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