Anup Patel 0ffc1a9522 hw/riscv: virt: Re-factor FDT generation ... We re-factor and break the FDT generation into smaller functions so that it is easier to modify FDT generation for different configurations of virt machine. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210831110603.338681-4-anup.patel@wdc.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2021-09-21 07:56:49 +10:00
..
boot.c	hw/riscv/boot: Check the error of fdt_pack()	2021-07-15 09:35:46 +10:00
Kconfig	hw/intc: Rename sifive_clint sources to riscv_aclint sources	2021-09-21 07:56:49 +10:00
meson.build	hw/riscv/Kconfig: Restrict NUMA to Virt & Spike machines	2021-07-20 15:32:49 +02:00
microchip_pfsoc.c	hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT	2021-09-21 07:56:49 +10:00
numa.c	hw: Do not include qemu/log.h if it is not necessary	2021-05-02 17:24:50 +02:00
opentitan.c	hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines	2021-09-21 07:56:49 +10:00
riscv_hart.c	hw/riscv: hart: Add a new 'resetvec' property	2020-09-09 15:54:18 -07:00
shakti_c.c	hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT	2021-09-21 07:56:49 +10:00
sifive_e.c	hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT	2021-09-21 07:56:49 +10:00
sifive_u.c	hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT	2021-09-21 07:56:49 +10:00
spike.c	hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT	2021-09-21 07:56:49 +10:00
virt.c	hw/riscv: virt: Re-factor FDT generation	2021-09-21 07:56:49 +10:00