msi_init() reports errors with error_report(), which is wrong when it's used in realize(). Fix by converting it to Error. Fix its callers to handle failure instead of ignoring it. For those callers who don't handle the failure, it might happen: when user want msi on, but he doesn't get what he want because of msi_init fails silently. cc: Gerd Hoffmann <kraxel@redhat.com> cc: John Snow <jsnow@redhat.com> cc: Dmitry Fleytman <dmitry@daynix.com> cc: Jason Wang <jasowang@redhat.com> cc: Michael S. Tsirkin <mst@redhat.com> cc: Hannes Reinecke <hare@suse.de> cc: Paolo Bonzini <pbonzini@redhat.com> cc: Alex Williamson <alex.williamson@redhat.com> cc: Markus Armbruster <armbru@redhat.com> cc: Marcel Apfelbaum <marcel@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Cao jin <caoj.fnst@cn.fujitsu.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Hannes Reinecke <hare@suse.com>
187 lines
5.2 KiB
C
187 lines
5.2 KiB
C
/*
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* xio3130_upstream.c
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* TI X3130 pci express upstream port switch
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*
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* Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
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* VA Linux Systems Japan K.K.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "hw/pci/pci_ids.h"
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#include "hw/pci/msi.h"
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#include "hw/pci/pcie.h"
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#include "xio3130_upstream.h"
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#include "qapi/error.h"
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#define PCI_DEVICE_ID_TI_XIO3130U 0x8232 /* upstream port */
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#define XIO3130_REVISION 0x2
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#define XIO3130_MSI_OFFSET 0x70
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#define XIO3130_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_64BIT
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#define XIO3130_MSI_NR_VECTOR 1
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#define XIO3130_SSVID_OFFSET 0x80
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#define XIO3130_SSVID_SVID 0
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#define XIO3130_SSVID_SSID 0
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#define XIO3130_EXP_OFFSET 0x90
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#define XIO3130_AER_OFFSET 0x100
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static void xio3130_upstream_write_config(PCIDevice *d, uint32_t address,
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uint32_t val, int len)
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{
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pci_bridge_write_config(d, address, val, len);
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pcie_cap_flr_write_config(d, address, val, len);
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pcie_aer_write_config(d, address, val, len);
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}
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static void xio3130_upstream_reset(DeviceState *qdev)
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{
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PCIDevice *d = PCI_DEVICE(qdev);
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pci_bridge_reset(qdev);
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pcie_cap_deverr_reset(d);
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}
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static int xio3130_upstream_initfn(PCIDevice *d)
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{
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PCIEPort *p = PCIE_PORT(d);
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int rc;
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Error *err = NULL;
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pci_bridge_initfn(d, TYPE_PCIE_BUS);
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pcie_port_init_reg(d);
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rc = msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR,
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XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
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XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT, &err);
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if (rc < 0) {
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assert(rc == -ENOTSUP);
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error_report_err(err);
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goto err_bridge;
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}
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rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET,
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XIO3130_SSVID_SVID, XIO3130_SSVID_SSID);
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if (rc < 0) {
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goto err_bridge;
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}
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rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_UPSTREAM,
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p->port);
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if (rc < 0) {
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goto err_msi;
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}
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pcie_cap_flr_init(d);
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pcie_cap_deverr_init(d);
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rc = pcie_aer_init(d, XIO3130_AER_OFFSET, PCI_ERR_SIZEOF);
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if (rc < 0) {
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goto err;
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}
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return 0;
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err:
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pcie_cap_exit(d);
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err_msi:
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msi_uninit(d);
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err_bridge:
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pci_bridge_exitfn(d);
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return rc;
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}
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static void xio3130_upstream_exitfn(PCIDevice *d)
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{
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pcie_aer_exit(d);
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pcie_cap_exit(d);
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msi_uninit(d);
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pci_bridge_exitfn(d);
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}
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PCIEPort *xio3130_upstream_init(PCIBus *bus, int devfn, bool multifunction,
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const char *bus_name, pci_map_irq_fn map_irq,
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uint8_t port)
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{
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PCIDevice *d;
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PCIBridge *br;
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DeviceState *qdev;
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d = pci_create_multifunction(bus, devfn, multifunction, "x3130-upstream");
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if (!d) {
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return NULL;
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}
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br = PCI_BRIDGE(d);
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qdev = DEVICE(d);
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pci_bridge_map_irq(br, bus_name, map_irq);
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qdev_prop_set_uint8(qdev, "port", port);
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qdev_init_nofail(qdev);
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return PCIE_PORT(d);
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}
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static const VMStateDescription vmstate_xio3130_upstream = {
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.name = "xio3130-express-upstream-port",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_PCIE_DEVICE(parent_obj.parent_obj, PCIEPort),
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VMSTATE_STRUCT(parent_obj.parent_obj.exp.aer_log, PCIEPort, 0,
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vmstate_pcie_aer_log, PCIEAERLog),
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VMSTATE_END_OF_LIST()
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}
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};
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static void xio3130_upstream_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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k->is_express = 1;
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k->is_bridge = 1;
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k->config_write = xio3130_upstream_write_config;
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k->init = xio3130_upstream_initfn;
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k->exit = xio3130_upstream_exitfn;
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k->vendor_id = PCI_VENDOR_ID_TI;
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k->device_id = PCI_DEVICE_ID_TI_XIO3130U;
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k->revision = XIO3130_REVISION;
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set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
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dc->desc = "TI X3130 Upstream Port of PCI Express Switch";
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dc->reset = xio3130_upstream_reset;
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dc->vmsd = &vmstate_xio3130_upstream;
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}
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static const TypeInfo xio3130_upstream_info = {
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.name = "x3130-upstream",
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.parent = TYPE_PCIE_PORT,
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.class_init = xio3130_upstream_class_init,
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};
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static void xio3130_upstream_register_types(void)
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{
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type_register_static(&xio3130_upstream_info);
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}
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type_init(xio3130_upstream_register_types)
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/*
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* Local variables:
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* c-indent-level: 4
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* c-basic-offset: 4
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* tab-width: 8
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* indent-tab-mode: nil
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* End:
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*/
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