There is no "version 2" of the "Lesser" General Public License. It is either "GPL version 2.0" or "Lesser GPL version 2.1". This patch replaces all occurrences of "Lesser GPL version 2" with "Lesser GPL version 2.1" in comment section. Signed-off-by: Chetan Pant <chetan4windows@gmail.com> Message-Id: <20201023123353.19796-1-chetan4windows@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
249 lines
7.7 KiB
C
249 lines
7.7 KiB
C
/*
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* common defines for all CPUs
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef CPU_DEFS_H
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#define CPU_DEFS_H
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#ifndef NEED_CPU_H
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#error cpu.h included from common code
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#endif
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#include "qemu/host-utils.h"
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#include "qemu/thread.h"
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#ifdef CONFIG_TCG
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#include "tcg-target.h"
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#endif
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#ifndef CONFIG_USER_ONLY
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#include "exec/hwaddr.h"
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#endif
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#include "exec/memattrs.h"
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#include "hw/core/cpu.h"
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#include "cpu-param.h"
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#ifndef TARGET_LONG_BITS
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# error TARGET_LONG_BITS must be defined in cpu-param.h
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#endif
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#ifndef NB_MMU_MODES
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# error NB_MMU_MODES must be defined in cpu-param.h
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#endif
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#ifndef TARGET_PHYS_ADDR_SPACE_BITS
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# error TARGET_PHYS_ADDR_SPACE_BITS must be defined in cpu-param.h
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#endif
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#ifndef TARGET_VIRT_ADDR_SPACE_BITS
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# error TARGET_VIRT_ADDR_SPACE_BITS must be defined in cpu-param.h
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#endif
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#ifndef TARGET_PAGE_BITS
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# ifdef TARGET_PAGE_BITS_VARY
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# ifndef TARGET_PAGE_BITS_MIN
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# error TARGET_PAGE_BITS_MIN must be defined in cpu-param.h
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# endif
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# else
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# error TARGET_PAGE_BITS must be defined in cpu-param.h
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# endif
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#endif
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#define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)
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/* target_ulong is the type of a virtual address */
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#if TARGET_LONG_SIZE == 4
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typedef int32_t target_long;
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typedef uint32_t target_ulong;
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#define TARGET_FMT_lx "%08x"
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#define TARGET_FMT_ld "%d"
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#define TARGET_FMT_lu "%u"
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#elif TARGET_LONG_SIZE == 8
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typedef int64_t target_long;
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typedef uint64_t target_ulong;
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#define TARGET_FMT_lx "%016" PRIx64
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#define TARGET_FMT_ld "%" PRId64
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#define TARGET_FMT_lu "%" PRIu64
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#else
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#error TARGET_LONG_SIZE undefined
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#endif
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#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
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/* use a fully associative victim tlb of 8 entries */
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#define CPU_VTLB_SIZE 8
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#if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32
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#define CPU_TLB_ENTRY_BITS 4
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#else
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#define CPU_TLB_ENTRY_BITS 5
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#endif
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#define CPU_TLB_DYN_MIN_BITS 6
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#define CPU_TLB_DYN_DEFAULT_BITS 8
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# if HOST_LONG_BITS == 32
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/* Make sure we do not require a double-word shift for the TLB load */
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# define CPU_TLB_DYN_MAX_BITS (32 - TARGET_PAGE_BITS)
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# else /* HOST_LONG_BITS == 64 */
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/*
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* Assuming TARGET_PAGE_BITS==12, with 2**22 entries we can cover 2**(22+12) ==
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* 2**34 == 16G of address space. This is roughly what one would expect a
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* TLB to cover in a modern (as of 2018) x86_64 CPU. For instance, Intel
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* Skylake's Level-2 STLB has 16 1G entries.
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* Also, make sure we do not size the TLB past the guest's address space.
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*/
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# ifdef TARGET_PAGE_BITS_VARY
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# define CPU_TLB_DYN_MAX_BITS \
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MIN(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS)
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# else
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# define CPU_TLB_DYN_MAX_BITS \
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MIN_CONST(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS)
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# endif
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# endif
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typedef struct CPUTLBEntry {
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/* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address
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bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not
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go directly to ram.
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bit 3 : indicates that the entry is invalid
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bit 2..0 : zero
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*/
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union {
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struct {
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target_ulong addr_read;
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target_ulong addr_write;
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target_ulong addr_code;
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/* Addend to virtual address to get host address. IO accesses
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use the corresponding iotlb value. */
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uintptr_t addend;
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};
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/* padding to get a power of two size */
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uint8_t dummy[1 << CPU_TLB_ENTRY_BITS];
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};
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} CPUTLBEntry;
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QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS));
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/* The IOTLB is not accessed directly inline by generated TCG code,
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* so the CPUIOTLBEntry layout is not as critical as that of the
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* CPUTLBEntry. (This is also why we don't want to combine the two
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* structs into one.)
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*/
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typedef struct CPUIOTLBEntry {
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/*
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* @addr contains:
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* - in the lower TARGET_PAGE_BITS, a physical section number
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* - with the lower TARGET_PAGE_BITS masked off, an offset which
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* must be added to the virtual address to obtain:
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* + the ram_addr_t of the target RAM (if the physical section
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* number is PHYS_SECTION_NOTDIRTY or PHYS_SECTION_ROM)
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* + the offset within the target MemoryRegion (otherwise)
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*/
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hwaddr addr;
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MemTxAttrs attrs;
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} CPUIOTLBEntry;
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/*
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* Data elements that are per MMU mode, minus the bits accessed by
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* the TCG fast path.
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*/
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typedef struct CPUTLBDesc {
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/*
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* Describe a region covering all of the large pages allocated
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* into the tlb. When any page within this region is flushed,
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* we must flush the entire tlb. The region is matched if
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* (addr & large_page_mask) == large_page_addr.
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*/
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target_ulong large_page_addr;
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target_ulong large_page_mask;
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/* host time (in ns) at the beginning of the time window */
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int64_t window_begin_ns;
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/* maximum number of entries observed in the window */
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size_t window_max_entries;
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size_t n_used_entries;
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/* The next index to use in the tlb victim table. */
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size_t vindex;
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/* The tlb victim table, in two parts. */
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CPUTLBEntry vtable[CPU_VTLB_SIZE];
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CPUIOTLBEntry viotlb[CPU_VTLB_SIZE];
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/* The iotlb. */
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CPUIOTLBEntry *iotlb;
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} CPUTLBDesc;
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/*
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* Data elements that are per MMU mode, accessed by the fast path.
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* The structure is aligned to aid loading the pair with one insn.
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*/
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typedef struct CPUTLBDescFast {
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/* Contains (n_entries - 1) << CPU_TLB_ENTRY_BITS */
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uintptr_t mask;
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/* The array of tlb entries itself. */
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CPUTLBEntry *table;
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} CPUTLBDescFast QEMU_ALIGNED(2 * sizeof(void *));
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/*
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* Data elements that are shared between all MMU modes.
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*/
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typedef struct CPUTLBCommon {
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/* Serialize updates to f.table and d.vtable, and others as noted. */
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QemuSpin lock;
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/*
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* Within dirty, for each bit N, modifications have been made to
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* mmu_idx N since the last time that mmu_idx was flushed.
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* Protected by tlb_c.lock.
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*/
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uint16_t dirty;
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/*
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* Statistics. These are not lock protected, but are read and
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* written atomically. This allows the monitor to print a snapshot
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* of the stats without interfering with the cpu.
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*/
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size_t full_flush_count;
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size_t part_flush_count;
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size_t elide_flush_count;
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} CPUTLBCommon;
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/*
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* The entire softmmu tlb, for all MMU modes.
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* The meaning of each of the MMU modes is defined in the target code.
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* Since this is placed within CPUNegativeOffsetState, the smallest
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* negative offsets are at the end of the struct.
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*/
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typedef struct CPUTLB {
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CPUTLBCommon c;
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CPUTLBDesc d[NB_MMU_MODES];
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CPUTLBDescFast f[NB_MMU_MODES];
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} CPUTLB;
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/* This will be used by TCG backends to compute offsets. */
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#define TLB_MASK_TABLE_OFS(IDX) \
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((int)offsetof(ArchCPU, neg.tlb.f[IDX]) - (int)offsetof(ArchCPU, env))
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#else
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typedef struct CPUTLB { } CPUTLB;
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#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
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/*
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* This structure must be placed in ArchCPU immediately
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* before CPUArchState, as a field named "neg".
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*/
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typedef struct CPUNegativeOffsetState {
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CPUTLB tlb;
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IcountDecr icount_decr;
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} CPUNegativeOffsetState;
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#endif
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