Add helpers for instructions that need to interact with QEMU. Also, add stubs for unimplemented instructions. Instructions SPM and WDR are left unimplemented because they require emulation of complex peripherals. The implementation of instruction SLEEP is very limited due to the lack of peripherals to generate wake interrupts. Memory access instructions are implemented here because some address ranges actually refer to CPU registers. Signed-off-by: Michael Rolnik <mrolnik@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com> Signed-off-by: Thomas Huth <huth@tuxfamily.org> Message-Id: <20200705140315.260514-10-huth@tuxfamily.org> [PMD: Replace cpu_physical_memory() API by address_space_ldst() API to fix running on big-endian host, reported and suggested by Peter Maydell] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
349 lines
9.7 KiB
C
349 lines
9.7 KiB
C
/*
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* QEMU AVR CPU helpers
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*
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* Copyright (c) 2016-2020 Michael Rolnik
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "exec/address-spaces.h"
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#include "exec/helper-proto.h"
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bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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{
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bool ret = false;
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CPUClass *cc = CPU_GET_CLASS(cs);
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AVRCPU *cpu = AVR_CPU(cs);
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CPUAVRState *env = &cpu->env;
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if (interrupt_request & CPU_INTERRUPT_RESET) {
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if (cpu_interrupts_enabled(env)) {
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cs->exception_index = EXCP_RESET;
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cc->do_interrupt(cs);
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cs->interrupt_request &= ~CPU_INTERRUPT_RESET;
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ret = true;
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}
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}
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if (interrupt_request & CPU_INTERRUPT_HARD) {
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if (cpu_interrupts_enabled(env) && env->intsrc != 0) {
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int index = ctz32(env->intsrc);
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cs->exception_index = EXCP_INT(index);
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cc->do_interrupt(cs);
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env->intsrc &= env->intsrc - 1; /* clear the interrupt */
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cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
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ret = true;
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}
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}
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return ret;
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}
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void avr_cpu_do_interrupt(CPUState *cs)
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{
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AVRCPU *cpu = AVR_CPU(cs);
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CPUAVRState *env = &cpu->env;
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uint32_t ret = env->pc_w;
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int vector = 0;
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int size = avr_feature(env, AVR_FEATURE_JMP_CALL) ? 2 : 1;
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int base = 0;
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if (cs->exception_index == EXCP_RESET) {
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vector = 0;
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} else if (env->intsrc != 0) {
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vector = ctz32(env->intsrc) + 1;
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}
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if (avr_feature(env, AVR_FEATURE_3_BYTE_PC)) {
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cpu_stb_data(env, env->sp--, (ret & 0x0000ff));
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cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >> 8);
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cpu_stb_data(env, env->sp--, (ret & 0xff0000) >> 16);
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} else if (avr_feature(env, AVR_FEATURE_2_BYTE_PC)) {
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cpu_stb_data(env, env->sp--, (ret & 0x0000ff));
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cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >> 8);
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} else {
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cpu_stb_data(env, env->sp--, (ret & 0x0000ff));
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}
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env->pc_w = base + vector * size;
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env->sregI = 0; /* clear Global Interrupt Flag */
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cs->exception_index = -1;
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}
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int avr_cpu_memory_rw_debug(CPUState *cs, vaddr addr, uint8_t *buf,
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int len, bool is_write)
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{
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return cpu_memory_rw_debug(cs, addr, buf, len, is_write);
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}
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hwaddr avr_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
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{
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return addr; /* I assume 1:1 address correspondance */
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}
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bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr)
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{
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int prot = 0;
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MemTxAttrs attrs = {};
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uint32_t paddr;
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address &= TARGET_PAGE_MASK;
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if (mmu_idx == MMU_CODE_IDX) {
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/* access to code in flash */
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paddr = OFFSET_CODE + address;
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prot = PAGE_READ | PAGE_EXEC;
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if (paddr + TARGET_PAGE_SIZE > OFFSET_DATA) {
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error_report("execution left flash memory");
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abort();
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}
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} else if (address < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) {
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/*
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* access to CPU registers, exit and rebuilt this TB to use full access
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* incase it touches specially handled registers like SREG or SP
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*/
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AVRCPU *cpu = AVR_CPU(cs);
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CPUAVRState *env = &cpu->env;
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env->fullacc = 1;
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cpu_loop_exit_restore(cs, retaddr);
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} else {
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/* access to memory. nothing special */
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paddr = OFFSET_DATA + address;
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prot = PAGE_READ | PAGE_WRITE;
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}
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tlb_set_page_with_attrs(cs, address, paddr, attrs, prot,
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mmu_idx, TARGET_PAGE_SIZE);
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return true;
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}
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/*
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* helpers
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*/
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void helper_sleep(CPUAVRState *env)
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{
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CPUState *cs = env_cpu(env);
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cs->exception_index = EXCP_HLT;
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cpu_loop_exit(cs);
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}
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void helper_unsupported(CPUAVRState *env)
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{
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CPUState *cs = env_cpu(env);
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/*
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* I count not find what happens on the real platform, so
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* it's EXCP_DEBUG for meanwhile
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*/
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cs->exception_index = EXCP_DEBUG;
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if (qemu_loglevel_mask(LOG_UNIMP)) {
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qemu_log("UNSUPPORTED\n");
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cpu_dump_state(cs, stderr, 0);
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}
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cpu_loop_exit(cs);
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}
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void helper_debug(CPUAVRState *env)
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{
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CPUState *cs = env_cpu(env);
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cs->exception_index = EXCP_DEBUG;
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cpu_loop_exit(cs);
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}
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void helper_break(CPUAVRState *env)
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{
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CPUState *cs = env_cpu(env);
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cs->exception_index = EXCP_DEBUG;
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cpu_loop_exit(cs);
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}
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void helper_wdr(CPUAVRState *env)
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{
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CPUState *cs = env_cpu(env);
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/* WD is not implemented yet, placeholder */
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cs->exception_index = EXCP_DEBUG;
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cpu_loop_exit(cs);
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}
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/*
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* This function implements IN instruction
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*
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* It does the following
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* a. if an IO register belongs to CPU, its value is read and returned
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* b. otherwise io address is translated to mem address and physical memory
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* is read.
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* c. it caches the value for sake of SBI, SBIC, SBIS & CBI implementation
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*
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*/
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target_ulong helper_inb(CPUAVRState *env, uint32_t port)
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{
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target_ulong data = 0;
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switch (port) {
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case 0x38: /* RAMPD */
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data = 0xff & (env->rampD >> 16);
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break;
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case 0x39: /* RAMPX */
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data = 0xff & (env->rampX >> 16);
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break;
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case 0x3a: /* RAMPY */
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data = 0xff & (env->rampY >> 16);
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break;
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case 0x3b: /* RAMPZ */
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data = 0xff & (env->rampZ >> 16);
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break;
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case 0x3c: /* EIND */
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data = 0xff & (env->eind >> 16);
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break;
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case 0x3d: /* SPL */
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data = env->sp & 0x00ff;
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break;
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case 0x3e: /* SPH */
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data = env->sp >> 8;
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break;
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case 0x3f: /* SREG */
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data = cpu_get_sreg(env);
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break;
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default:
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/* not a special register, pass to normal memory access */
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data = address_space_ldub(&address_space_memory,
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OFFSET_IO_REGISTERS + port,
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MEMTXATTRS_UNSPECIFIED, NULL);
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}
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return data;
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}
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/*
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* This function implements OUT instruction
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*
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* It does the following
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* a. if an IO register belongs to CPU, its value is written into the register
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* b. otherwise io address is translated to mem address and physical memory
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* is written.
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* c. it caches the value for sake of SBI, SBIC, SBIS & CBI implementation
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*
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*/
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void helper_outb(CPUAVRState *env, uint32_t port, uint32_t data)
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{
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data &= 0x000000ff;
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switch (port) {
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case 0x38: /* RAMPD */
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if (avr_feature(env, AVR_FEATURE_RAMPD)) {
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env->rampD = (data & 0xff) << 16;
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}
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break;
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case 0x39: /* RAMPX */
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if (avr_feature(env, AVR_FEATURE_RAMPX)) {
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env->rampX = (data & 0xff) << 16;
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}
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break;
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case 0x3a: /* RAMPY */
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if (avr_feature(env, AVR_FEATURE_RAMPY)) {
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env->rampY = (data & 0xff) << 16;
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}
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break;
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case 0x3b: /* RAMPZ */
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if (avr_feature(env, AVR_FEATURE_RAMPZ)) {
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env->rampZ = (data & 0xff) << 16;
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}
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break;
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case 0x3c: /* EIDN */
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env->eind = (data & 0xff) << 16;
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break;
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case 0x3d: /* SPL */
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env->sp = (env->sp & 0xff00) | (data);
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break;
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case 0x3e: /* SPH */
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if (avr_feature(env, AVR_FEATURE_2_BYTE_SP)) {
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env->sp = (env->sp & 0x00ff) | (data << 8);
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}
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break;
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case 0x3f: /* SREG */
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cpu_set_sreg(env, data);
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break;
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default:
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/* not a special register, pass to normal memory access */
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address_space_stb(&address_space_memory, OFFSET_IO_REGISTERS + port,
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data, MEMTXATTRS_UNSPECIFIED, NULL);
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}
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}
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/*
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* this function implements LD instruction when there is a posibility to read
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* from a CPU register
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*/
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target_ulong helper_fullrd(CPUAVRState *env, uint32_t addr)
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{
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uint8_t data;
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env->fullacc = false;
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if (addr < NUMBER_OF_CPU_REGISTERS) {
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/* CPU registers */
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data = env->r[addr];
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} else if (addr < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) {
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/* IO registers */
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data = helper_inb(env, addr - NUMBER_OF_CPU_REGISTERS);
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} else {
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/* memory */
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data = address_space_ldub(&address_space_memory, OFFSET_DATA + addr,
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MEMTXATTRS_UNSPECIFIED, NULL);
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}
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return data;
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}
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/*
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* this function implements ST instruction when there is a posibility to write
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* into a CPU register
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*/
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void helper_fullwr(CPUAVRState *env, uint32_t data, uint32_t addr)
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{
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env->fullacc = false;
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/* Following logic assumes this: */
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assert(OFFSET_CPU_REGISTERS == OFFSET_DATA);
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assert(OFFSET_IO_REGISTERS == OFFSET_CPU_REGISTERS +
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NUMBER_OF_CPU_REGISTERS);
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if (addr < NUMBER_OF_CPU_REGISTERS) {
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/* CPU registers */
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env->r[addr] = data;
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} else if (addr < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) {
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/* IO registers */
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helper_outb(env, addr - NUMBER_OF_CPU_REGISTERS, data);
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} else {
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/* memory */
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address_space_stb(&address_space_memory, OFFSET_DATA + addr, data,
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MEMTXATTRS_UNSPECIFIED, NULL);
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}
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}
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