The set of large pages in the kernel is probably not the same as the set of large pages in the application. Forcing one range to cover both will flush more often than necessary. This allows tlb_flush_page_async_work to flush just the one mmu_idx implicated, which in turn allows us to remove tlb_check_page_and_flush_by_mmuidx_async_work. Tested-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
196 lines
7.1 KiB
C
196 lines
7.1 KiB
C
/*
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* common defines for all CPUs
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef CPU_DEFS_H
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#define CPU_DEFS_H
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#ifndef NEED_CPU_H
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#error cpu.h included from common code
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#endif
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#include "qemu/host-utils.h"
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#include "qemu/thread.h"
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#include "qemu/queue.h"
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#ifdef CONFIG_TCG
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#include "tcg-target.h"
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#endif
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#ifndef CONFIG_USER_ONLY
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#include "exec/hwaddr.h"
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#endif
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#include "exec/memattrs.h"
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#ifndef TARGET_LONG_BITS
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#error TARGET_LONG_BITS must be defined before including this header
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#endif
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#define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)
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/* target_ulong is the type of a virtual address */
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#if TARGET_LONG_SIZE == 4
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typedef int32_t target_long;
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typedef uint32_t target_ulong;
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#define TARGET_FMT_lx "%08x"
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#define TARGET_FMT_ld "%d"
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#define TARGET_FMT_lu "%u"
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#elif TARGET_LONG_SIZE == 8
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typedef int64_t target_long;
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typedef uint64_t target_ulong;
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#define TARGET_FMT_lx "%016" PRIx64
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#define TARGET_FMT_ld "%" PRId64
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#define TARGET_FMT_lu "%" PRIu64
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#else
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#error TARGET_LONG_SIZE undefined
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#endif
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#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
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/* use a fully associative victim tlb of 8 entries */
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#define CPU_VTLB_SIZE 8
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#if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32
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#define CPU_TLB_ENTRY_BITS 4
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#else
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#define CPU_TLB_ENTRY_BITS 5
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#endif
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/* TCG_TARGET_TLB_DISPLACEMENT_BITS is used in CPU_TLB_BITS to ensure that
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* the TLB is not unnecessarily small, but still small enough for the
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* TLB lookup instruction sequence used by the TCG target.
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*
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* TCG will have to generate an operand as large as the distance between
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* env and the tlb_table[NB_MMU_MODES - 1][0].addend. For simplicity,
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* the TCG targets just round everything up to the next power of two, and
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* count bits. This works because: 1) the size of each TLB is a largish
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* power of two, 2) and because the limit of the displacement is really close
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* to a power of two, 3) the offset of tlb_table[0][0] inside env is smaller
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* than the size of a TLB.
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*
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* For example, the maximum displacement 0xFFF0 on PPC and MIPS, but TCG
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* just says "the displacement is 16 bits". TCG_TARGET_TLB_DISPLACEMENT_BITS
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* then ensures that tlb_table at least 0x8000 bytes large ("not unnecessarily
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* small": 2^15). The operand then will come up smaller than 0xFFF0 without
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* any particular care, because the TLB for a single MMU mode is larger than
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* 0x10000-0xFFF0=16 bytes. In the end, the maximum value of the operand
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* could be something like 0xC000 (the offset of the last TLB table) plus
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* 0x18 (the offset of the addend field in each TLB entry) plus the offset
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* of tlb_table inside env (which is non-trivial but not huge).
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*/
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#define CPU_TLB_BITS \
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MIN(8, \
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TCG_TARGET_TLB_DISPLACEMENT_BITS - CPU_TLB_ENTRY_BITS - \
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(NB_MMU_MODES <= 1 ? 0 : \
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NB_MMU_MODES <= 2 ? 1 : \
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NB_MMU_MODES <= 4 ? 2 : \
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NB_MMU_MODES <= 8 ? 3 : 4))
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#define CPU_TLB_SIZE (1 << CPU_TLB_BITS)
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typedef struct CPUTLBEntry {
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/* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address
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bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not
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go directly to ram.
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bit 3 : indicates that the entry is invalid
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bit 2..0 : zero
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*/
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union {
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struct {
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target_ulong addr_read;
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target_ulong addr_write;
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target_ulong addr_code;
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/* Addend to virtual address to get host address. IO accesses
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use the corresponding iotlb value. */
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uintptr_t addend;
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};
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/* padding to get a power of two size */
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uint8_t dummy[1 << CPU_TLB_ENTRY_BITS];
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};
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} CPUTLBEntry;
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QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS));
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/* The IOTLB is not accessed directly inline by generated TCG code,
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* so the CPUIOTLBEntry layout is not as critical as that of the
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* CPUTLBEntry. (This is also why we don't want to combine the two
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* structs into one.)
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*/
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typedef struct CPUIOTLBEntry {
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/*
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* @addr contains:
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* - in the lower TARGET_PAGE_BITS, a physical section number
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* - with the lower TARGET_PAGE_BITS masked off, an offset which
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* must be added to the virtual address to obtain:
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* + the ram_addr_t of the target RAM (if the physical section
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* number is PHYS_SECTION_NOTDIRTY or PHYS_SECTION_ROM)
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* + the offset within the target MemoryRegion (otherwise)
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*/
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hwaddr addr;
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MemTxAttrs attrs;
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} CPUIOTLBEntry;
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typedef struct CPUTLBDesc {
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/*
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* Describe a region covering all of the large pages allocated
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* into the tlb. When any page within this region is flushed,
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* we must flush the entire tlb. The region is matched if
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* (addr & large_page_mask) == large_page_addr.
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*/
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target_ulong large_page_addr;
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target_ulong large_page_mask;
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} CPUTLBDesc;
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/*
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* Data elements that are shared between all MMU modes.
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*/
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typedef struct CPUTLBCommon {
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/* Serialize updates to tlb_table and tlb_v_table, and others as noted. */
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QemuSpin lock;
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/*
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* Within pending_flush, for each bit N, there exists an outstanding
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* cross-cpu flush for mmu_idx N. Further cross-cpu flushes to that
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* mmu_idx may be discarded. Protected by tlb_c.lock.
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*/
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uint16_t pending_flush;
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} CPUTLBCommon;
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/*
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* The meaning of each of the MMU modes is defined in the target code.
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* Note that NB_MMU_MODES is not yet defined; we can only reference it
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* within preprocessor defines that will be expanded later.
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*/
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#define CPU_COMMON_TLB \
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CPUTLBCommon tlb_c; \
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CPUTLBDesc tlb_d[NB_MMU_MODES]; \
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CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \
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CPUTLBEntry tlb_v_table[NB_MMU_MODES][CPU_VTLB_SIZE]; \
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CPUIOTLBEntry iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \
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CPUIOTLBEntry iotlb_v[NB_MMU_MODES][CPU_VTLB_SIZE]; \
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size_t tlb_flush_count; \
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target_ulong vtlb_index; \
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#else
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#define CPU_COMMON_TLB
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#endif
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#define CPU_COMMON \
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/* soft mmu support */ \
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CPU_COMMON_TLB \
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#endif
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