268fcca66b
Vector AMOs operate as if aq and rl bits were zero on each element with regard to ordering relative to other instructions in the same hart. Vector AMOs provide no ordering guarantee between element operations in the same vector AMO instruction Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200701152549.1218-10-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
31 lines
1,018 B
C
31 lines
1,018 B
C
/*
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* QEMU RISC-V CPU -- internal functions and types
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*
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* Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef RISCV_CPU_INTERNALS_H
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#define RISCV_CPU_INTERNALS_H
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#include "hw/registerfields.h"
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/* share data between vector helpers and decode code */
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FIELD(VDATA, MLEN, 0, 8)
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FIELD(VDATA, VM, 8, 1)
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FIELD(VDATA, LMUL, 9, 2)
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FIELD(VDATA, NF, 11, 4)
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FIELD(VDATA, WD, 11, 1)
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#endif
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