2bece2c883
Some hosts (amd64, ia64) have an ABI that ignores the high bits of the 64-bit register when passing 32-bit arguments. Others require the value to be properly sign-extended for the type. I.e. "int32_t" must be sign-extended and "uint32_t" must be zero-extended to 64-bits. To effect this, extend the "sizemask" parameter to tcg_gen_callN to include the signedness of the type of each parameter. If the tcg target requires it, extend each 32-bit argument into a 64-bit temp and pass that to the function call. This ABI feature is required by sparc64, ppc64 and s390x. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
110 lines
3.2 KiB
C
110 lines
3.2 KiB
C
/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2008 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#define TCG_TARGET_PPC64 1
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#define TCG_TARGET_REG_BITS 64
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#define TCG_TARGET_WORDS_BIGENDIAN
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#define TCG_TARGET_NB_REGS 32
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enum {
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TCG_REG_R0 = 0,
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TCG_REG_R1,
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TCG_REG_R2,
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TCG_REG_R3,
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TCG_REG_R4,
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TCG_REG_R5,
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TCG_REG_R6,
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TCG_REG_R7,
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TCG_REG_R8,
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TCG_REG_R9,
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TCG_REG_R10,
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TCG_REG_R11,
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TCG_REG_R12,
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TCG_REG_R13,
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TCG_REG_R14,
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TCG_REG_R15,
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TCG_REG_R16,
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TCG_REG_R17,
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TCG_REG_R18,
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TCG_REG_R19,
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TCG_REG_R20,
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TCG_REG_R21,
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TCG_REG_R22,
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TCG_REG_R23,
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TCG_REG_R24,
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TCG_REG_R25,
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TCG_REG_R26,
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TCG_REG_R27,
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TCG_REG_R28,
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TCG_REG_R29,
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TCG_REG_R30,
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TCG_REG_R31
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};
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/* used for function call generation */
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#define TCG_REG_CALL_STACK TCG_REG_R1
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#define TCG_TARGET_STACK_ALIGN 16
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#define TCG_TARGET_CALL_STACK_OFFSET 48
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/* optional instructions */
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#define TCG_TARGET_HAS_div_i32
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/* #define TCG_TARGET_HAS_rot_i32 */
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#define TCG_TARGET_HAS_ext8s_i32
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#define TCG_TARGET_HAS_ext16s_i32
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/* #define TCG_TARGET_HAS_ext8u_i32 */
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/* #define TCG_TARGET_HAS_ext16u_i32 */
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/* #define TCG_TARGET_HAS_bswap16_i32 */
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/* #define TCG_TARGET_HAS_bswap32_i32 */
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/* #define TCG_TARGET_HAS_not_i32 */
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#define TCG_TARGET_HAS_neg_i32
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/* #define TCG_TARGET_HAS_andc_i32 */
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/* #define TCG_TARGET_HAS_orc_i32 */
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/* #define TCG_TARGET_HAS_eqv_i32 */
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/* #define TCG_TARGET_HAS_nand_i32 */
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/* #define TCG_TARGET_HAS_nor_i32 */
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#define TCG_TARGET_HAS_div_i64
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/* #define TCG_TARGET_HAS_rot_i64 */
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#define TCG_TARGET_HAS_ext8s_i64
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#define TCG_TARGET_HAS_ext16s_i64
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#define TCG_TARGET_HAS_ext32s_i64
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/* #define TCG_TARGET_HAS_ext8u_i64 */
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/* #define TCG_TARGET_HAS_ext16u_i64 */
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/* #define TCG_TARGET_HAS_ext32u_i64 */
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/* #define TCG_TARGET_HAS_bswap16_i64 */
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/* #define TCG_TARGET_HAS_bswap32_i64 */
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/* #define TCG_TARGET_HAS_bswap64_i64 */
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/* #define TCG_TARGET_HAS_not_i64 */
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#define TCG_TARGET_HAS_neg_i64
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/* #define TCG_TARGET_HAS_andc_i64 */
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/* #define TCG_TARGET_HAS_orc_i64 */
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/* #define TCG_TARGET_HAS_eqv_i64 */
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/* #define TCG_TARGET_HAS_nand_i64 */
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/* #define TCG_TARGET_HAS_nor_i64 */
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#define TCG_AREG0 TCG_REG_R27
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#define TCG_TARGET_HAS_GUEST_BASE
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#define TCG_TARGET_EXTEND_ARGS 1
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