In my "build everything" tree, changing hw/qdev-properties.h triggers a recompile of some 2700 out of 6600 objects (not counting tests and objects that don't depend on qemu/osdep.h). Many places including hw/qdev-properties.h (directly or via hw/qdev.h) actually need only hw/qdev-core.h. Include hw/qdev-core.h there instead. hw/qdev.h is actually pointless: all it does is include hw/qdev-core.h and hw/qdev-properties.h, which in turn includes hw/qdev-core.h. Replace the remaining uses of hw/qdev.h by hw/qdev-properties.h. While there, delete a few superfluous inclusions of hw/qdev-core.h. Touching hw/qdev-properties.h now recompiles some 1200 objects. Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: "Daniel P. Berrangé" <berrange@redhat.com> Cc: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20190812052359.30071-22-armbru@redhat.com>
191 lines
5.7 KiB
C
191 lines
5.7 KiB
C
/*
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* x3130_downstream.c
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* TI X3130 pci express downstream port switch
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*
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* Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
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* VA Linux Systems Japan K.K.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "hw/pci/pci_ids.h"
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#include "hw/pci/msi.h"
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#include "hw/pci/pcie.h"
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#include "hw/pci/pcie_port.h"
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#include "hw/qdev-properties.h"
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#include "migration/vmstate.h"
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#include "qapi/error.h"
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#include "qemu/module.h"
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#define PCI_DEVICE_ID_TI_XIO3130D 0x8233 /* downstream port */
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#define XIO3130_REVISION 0x1
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#define XIO3130_MSI_OFFSET 0x70
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#define XIO3130_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_64BIT
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#define XIO3130_MSI_NR_VECTOR 1
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#define XIO3130_SSVID_OFFSET 0x80
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#define XIO3130_SSVID_SVID 0
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#define XIO3130_SSVID_SSID 0
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#define XIO3130_EXP_OFFSET 0x90
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#define XIO3130_AER_OFFSET 0x100
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static void xio3130_downstream_write_config(PCIDevice *d, uint32_t address,
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uint32_t val, int len)
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{
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uint16_t slt_ctl, slt_sta;
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pcie_cap_slot_get(d, &slt_ctl, &slt_sta);
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pci_bridge_write_config(d, address, val, len);
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pcie_cap_flr_write_config(d, address, val, len);
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pcie_cap_slot_write_config(d, slt_ctl, slt_sta, address, val, len);
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pcie_aer_write_config(d, address, val, len);
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}
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static void xio3130_downstream_reset(DeviceState *qdev)
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{
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PCIDevice *d = PCI_DEVICE(qdev);
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pcie_cap_deverr_reset(d);
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pcie_cap_slot_reset(d);
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pcie_cap_arifwd_reset(d);
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pci_bridge_reset(qdev);
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}
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static void xio3130_downstream_realize(PCIDevice *d, Error **errp)
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{
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PCIEPort *p = PCIE_PORT(d);
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PCIESlot *s = PCIE_SLOT(d);
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int rc;
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pci_bridge_initfn(d, TYPE_PCIE_BUS);
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pcie_port_init_reg(d);
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rc = msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR,
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XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
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XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT,
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errp);
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if (rc < 0) {
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assert(rc == -ENOTSUP);
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goto err_bridge;
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}
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rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET,
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XIO3130_SSVID_SVID, XIO3130_SSVID_SSID,
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errp);
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if (rc < 0) {
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goto err_bridge;
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}
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rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_DOWNSTREAM,
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p->port, errp);
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if (rc < 0) {
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goto err_msi;
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}
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pcie_cap_flr_init(d);
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pcie_cap_deverr_init(d);
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pcie_cap_slot_init(d, s->slot);
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pcie_cap_arifwd_init(d);
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pcie_chassis_create(s->chassis);
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rc = pcie_chassis_add_slot(s);
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if (rc < 0) {
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error_setg(errp, "Can't add chassis slot, error %d", rc);
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goto err_pcie_cap;
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}
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rc = pcie_aer_init(d, PCI_ERR_VER, XIO3130_AER_OFFSET,
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PCI_ERR_SIZEOF, errp);
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if (rc < 0) {
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goto err;
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}
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return;
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err:
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pcie_chassis_del_slot(s);
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err_pcie_cap:
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pcie_cap_exit(d);
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err_msi:
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msi_uninit(d);
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err_bridge:
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pci_bridge_exitfn(d);
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}
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static void xio3130_downstream_exitfn(PCIDevice *d)
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{
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PCIESlot *s = PCIE_SLOT(d);
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pcie_aer_exit(d);
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pcie_chassis_del_slot(s);
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pcie_cap_exit(d);
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msi_uninit(d);
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pci_bridge_exitfn(d);
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}
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static Property xio3130_downstream_props[] = {
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DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present,
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QEMU_PCIE_SLTCAP_PCP_BITNR, true),
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DEFINE_PROP_END_OF_LIST()
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};
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static const VMStateDescription vmstate_xio3130_downstream = {
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.name = "xio3130-express-downstream-port",
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.priority = MIG_PRI_PCI_BUS,
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.version_id = 1,
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.minimum_version_id = 1,
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.post_load = pcie_cap_slot_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_PCI_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot),
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VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log,
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PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog),
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VMSTATE_END_OF_LIST()
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}
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};
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static void xio3130_downstream_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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k->is_bridge = true;
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k->config_write = xio3130_downstream_write_config;
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k->realize = xio3130_downstream_realize;
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k->exit = xio3130_downstream_exitfn;
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k->vendor_id = PCI_VENDOR_ID_TI;
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k->device_id = PCI_DEVICE_ID_TI_XIO3130D;
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k->revision = XIO3130_REVISION;
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set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
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dc->desc = "TI X3130 Downstream Port of PCI Express Switch";
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dc->reset = xio3130_downstream_reset;
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dc->vmsd = &vmstate_xio3130_downstream;
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dc->props = xio3130_downstream_props;
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}
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static const TypeInfo xio3130_downstream_info = {
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.name = "xio3130-downstream",
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.parent = TYPE_PCIE_SLOT,
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.class_init = xio3130_downstream_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_PCIE_DEVICE },
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{ }
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},
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};
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static void xio3130_downstream_register_types(void)
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{
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type_register_static(&xio3130_downstream_info);
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}
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type_init(xio3130_downstream_register_types)
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