The PowerISA v3.1 defines that if the proper bits are set (MMCR0_PMC1CE for PMC1 and MMCR0_PMCjCE for the remaining PMCs), counter negative conditions are enabled. This means that if the counter value overflows (i.e. exceeds 0x80000000) a performance monitor alert will occur. This alert can trigger an event-based exception (to be implemented in the next patches) if the MMCR0_EBE bit is set. For now, overflowing the counter when the PMC is counting cycles will just trigger a performance monitor alert. This is done by starting the overflow timer to expire in the moment the overflow would be occuring. The timer will call fire_PMC_interrupt() (via cpu_ppc_pmu_timer_cb) which will trigger the PMU alert and, if the conditions are met, an EBB exception. Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20211201151734.654994-6-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
265 lines
6.5 KiB
C
265 lines
6.5 KiB
C
/*
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* PMU emulation helpers for TCG IBM POWER chips
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*
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* Copyright IBM Corp. 2021
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*
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* Authors:
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* Daniel Henrique Barboza <danielhb413@gmail.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "power8-pmu.h"
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#include "cpu.h"
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#include "helper_regs.h"
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#include "exec/exec-all.h"
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#include "exec/helper-proto.h"
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#include "qemu/error-report.h"
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#include "qemu/main-loop.h"
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#include "hw/ppc/ppc.h"
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#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
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#define PMC_COUNTER_NEGATIVE_VAL 0x80000000UL
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static bool pmc_is_inactive(CPUPPCState *env, int sprn)
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{
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if (env->spr[SPR_POWER_MMCR0] & MMCR0_FC) {
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return true;
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}
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if (sprn < SPR_POWER_PMC5) {
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return env->spr[SPR_POWER_MMCR0] & MMCR0_FC14;
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}
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return env->spr[SPR_POWER_MMCR0] & MMCR0_FC56;
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}
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static bool pmc_has_overflow_enabled(CPUPPCState *env, int sprn)
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{
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if (sprn == SPR_POWER_PMC1) {
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return env->spr[SPR_POWER_MMCR0] & MMCR0_PMC1CE;
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}
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return env->spr[SPR_POWER_MMCR0] & MMCR0_PMCjCE;
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}
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/*
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* For PMCs 1-4, IBM POWER chips has support for an implementation
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* dependent event, 0x1E, that enables cycle counting. The Linux kernel
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* makes extensive use of 0x1E, so let's also support it.
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*
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* Likewise, event 0x2 is an implementation-dependent event that IBM
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* POWER chips implement (at least since POWER8) that is equivalent to
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* PM_INST_CMPL. Let's support this event on PMCs 1-4 as well.
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*/
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static PMUEventType pmc_get_event(CPUPPCState *env, int sprn)
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{
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uint8_t mmcr1_evt_extr[] = { MMCR1_PMC1EVT_EXTR, MMCR1_PMC2EVT_EXTR,
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MMCR1_PMC3EVT_EXTR, MMCR1_PMC4EVT_EXTR };
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PMUEventType evt_type = PMU_EVENT_INVALID;
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uint8_t pmcsel;
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int i;
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if (pmc_is_inactive(env, sprn)) {
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return PMU_EVENT_INACTIVE;
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}
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if (sprn == SPR_POWER_PMC5) {
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return PMU_EVENT_INSTRUCTIONS;
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}
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if (sprn == SPR_POWER_PMC6) {
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return PMU_EVENT_CYCLES;
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}
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i = sprn - SPR_POWER_PMC1;
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pmcsel = extract64(env->spr[SPR_POWER_MMCR1], mmcr1_evt_extr[i],
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MMCR1_EVT_SIZE);
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switch (pmcsel) {
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case 0x2:
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evt_type = PMU_EVENT_INSTRUCTIONS;
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break;
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case 0x1E:
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evt_type = PMU_EVENT_CYCLES;
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break;
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case 0xF0:
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/*
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* PMC1SEL = 0xF0 is the architected PowerISA v3.1
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* event that counts cycles using PMC1.
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*/
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if (sprn == SPR_POWER_PMC1) {
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evt_type = PMU_EVENT_CYCLES;
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}
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break;
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case 0xFE:
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/*
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* PMC1SEL = 0xFE is the architected PowerISA v3.1
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* event to sample instructions using PMC1.
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*/
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if (sprn == SPR_POWER_PMC1) {
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evt_type = PMU_EVENT_INSTRUCTIONS;
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}
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break;
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default:
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break;
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}
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return evt_type;
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}
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static void pmu_update_cycles(CPUPPCState *env)
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{
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uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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uint64_t time_delta = now - env->pmu_base_time;
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int sprn;
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for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC6; sprn++) {
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if (pmc_get_event(env, sprn) != PMU_EVENT_CYCLES) {
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continue;
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}
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/*
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* The pseries and powernv clock runs at 1Ghz, meaning
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* that 1 nanosec equals 1 cycle.
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*/
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env->spr[sprn] += time_delta;
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}
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/* Update base_time for future calculations */
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env->pmu_base_time = now;
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}
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/*
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* Helper function to retrieve the cycle overflow timer of the
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* 'sprn' counter.
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*/
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static QEMUTimer *get_cyc_overflow_timer(CPUPPCState *env, int sprn)
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{
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return env->pmu_cyc_overflow_timers[sprn - SPR_POWER_PMC1];
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}
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static void pmc_update_overflow_timer(CPUPPCState *env, int sprn)
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{
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QEMUTimer *pmc_overflow_timer = get_cyc_overflow_timer(env, sprn);
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int64_t timeout;
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/*
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* PMC5 does not have an overflow timer and this pointer
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* will be NULL.
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*/
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if (!pmc_overflow_timer) {
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return;
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}
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if (pmc_get_event(env, sprn) != PMU_EVENT_CYCLES ||
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!pmc_has_overflow_enabled(env, sprn)) {
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/* Overflow timer is not needed for this counter */
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timer_del(pmc_overflow_timer);
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return;
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}
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if (env->spr[sprn] >= PMC_COUNTER_NEGATIVE_VAL) {
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timeout = 0;
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} else {
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timeout = PMC_COUNTER_NEGATIVE_VAL - env->spr[sprn];
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}
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/*
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* Use timer_mod_anticipate() because an overflow timer might
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* be already running for this PMC.
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*/
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timer_mod_anticipate(pmc_overflow_timer, env->pmu_base_time + timeout);
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}
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static void pmu_update_overflow_timers(CPUPPCState *env)
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{
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int sprn;
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/*
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* Scroll through all PMCs and start counter overflow timers for
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* PM_CYC events, if needed.
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*/
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for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC6; sprn++) {
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pmc_update_overflow_timer(env, sprn);
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}
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}
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void helper_store_mmcr0(CPUPPCState *env, target_ulong value)
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{
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pmu_update_cycles(env);
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env->spr[SPR_POWER_MMCR0] = value;
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/* MMCR0 writes can change HFLAGS_PMCCCLEAR */
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hreg_compute_hflags(env);
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/* Update cycle overflow timers with the current MMCR0 state */
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pmu_update_overflow_timers(env);
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}
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void helper_store_mmcr1(CPUPPCState *env, uint64_t value)
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{
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pmu_update_cycles(env);
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env->spr[SPR_POWER_MMCR1] = value;
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}
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target_ulong helper_read_pmc(CPUPPCState *env, uint32_t sprn)
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{
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pmu_update_cycles(env);
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return env->spr[sprn];
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}
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void helper_store_pmc(CPUPPCState *env, uint32_t sprn, uint64_t value)
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{
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pmu_update_cycles(env);
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env->spr[sprn] = value;
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pmc_update_overflow_timer(env, sprn);
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}
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static void fire_PMC_interrupt(PowerPCCPU *cpu)
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{
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CPUPPCState *env = &cpu->env;
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if (!(env->spr[SPR_POWER_MMCR0] & MMCR0_EBE)) {
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return;
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}
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/* PMC interrupt not implemented yet */
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return;
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}
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static void cpu_ppc_pmu_timer_cb(void *opaque)
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{
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PowerPCCPU *cpu = opaque;
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fire_PMC_interrupt(cpu);
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}
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void cpu_ppc_pmu_init(CPUPPCState *env)
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{
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PowerPCCPU *cpu = env_archcpu(env);
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int i, sprn;
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for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC6; sprn++) {
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if (sprn == SPR_POWER_PMC5) {
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continue;
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}
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i = sprn - SPR_POWER_PMC1;
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env->pmu_cyc_overflow_timers[i] = timer_new_ns(QEMU_CLOCK_VIRTUAL,
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&cpu_ppc_pmu_timer_cb,
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cpu);
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}
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}
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#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
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