This converts existing DECLARE_OBJ_CHECKERS usage to OBJECT_DECLARE_TYPE when possible. $ ./scripts/codeconverter/converter.py -i \ --pattern=AddObjectDeclareType $(git grep -l '' -- '*.[ch]') Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Acked-by: Paul Durrant <paul@xen.org> Message-Id: <20200916182519.415636-5-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
179 lines
5.6 KiB
C
179 lines
5.6 KiB
C
/*
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* ARM SMMU Support
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*
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* Copyright (C) 2015-2016 Broadcom Corporation
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* Copyright (c) 2017 Red Hat, Inc.
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* Written by Prem Mallappa, Eric Auger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef HW_ARM_SMMU_COMMON_H
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#define HW_ARM_SMMU_COMMON_H
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#include "hw/sysbus.h"
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#include "hw/pci/pci.h"
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#include "qom/object.h"
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#define SMMU_PCI_BUS_MAX 256
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#define SMMU_PCI_DEVFN_MAX 256
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#define SMMU_PCI_DEVFN(sid) (sid & 0xFF)
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#define SMMU_MAX_VA_BITS 48
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/*
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* Page table walk error types
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*/
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typedef enum {
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SMMU_PTW_ERR_NONE,
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SMMU_PTW_ERR_WALK_EABT, /* Translation walk external abort */
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SMMU_PTW_ERR_TRANSLATION, /* Translation fault */
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SMMU_PTW_ERR_ADDR_SIZE, /* Address Size fault */
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SMMU_PTW_ERR_ACCESS, /* Access fault */
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SMMU_PTW_ERR_PERMISSION, /* Permission fault */
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} SMMUPTWEventType;
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typedef struct SMMUPTWEventInfo {
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SMMUPTWEventType type;
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dma_addr_t addr; /* fetched address that induced an abort, if any */
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} SMMUPTWEventInfo;
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typedef struct SMMUTransTableInfo {
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bool disabled; /* is the translation table disabled? */
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uint64_t ttb; /* TT base address */
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uint8_t tsz; /* input range, ie. 2^(64 -tsz)*/
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uint8_t granule_sz; /* granule page shift */
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bool had; /* hierarchical attribute disable */
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} SMMUTransTableInfo;
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typedef struct SMMUTLBEntry {
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IOMMUTLBEntry entry;
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uint8_t level;
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uint8_t granule;
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} SMMUTLBEntry;
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/*
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* Generic structure populated by derived SMMU devices
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* after decoding the configuration information and used as
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* input to the page table walk
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*/
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typedef struct SMMUTransCfg {
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int stage; /* translation stage */
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bool aa64; /* arch64 or aarch32 translation table */
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bool disabled; /* smmu is disabled */
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bool bypassed; /* translation is bypassed */
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bool aborted; /* translation is aborted */
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uint64_t ttb; /* TT base address */
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uint8_t oas; /* output address width */
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uint8_t tbi; /* Top Byte Ignore */
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uint16_t asid;
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SMMUTransTableInfo tt[2];
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uint32_t iotlb_hits; /* counts IOTLB hits for this asid */
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uint32_t iotlb_misses; /* counts IOTLB misses for this asid */
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} SMMUTransCfg;
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typedef struct SMMUDevice {
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void *smmu;
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PCIBus *bus;
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int devfn;
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IOMMUMemoryRegion iommu;
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AddressSpace as;
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uint32_t cfg_cache_hits;
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uint32_t cfg_cache_misses;
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QLIST_ENTRY(SMMUDevice) next;
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} SMMUDevice;
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typedef struct SMMUPciBus {
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PCIBus *bus;
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SMMUDevice *pbdev[]; /* Parent array is sparse, so dynamically alloc */
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} SMMUPciBus;
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typedef struct SMMUIOTLBKey {
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uint64_t iova;
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uint16_t asid;
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uint8_t tg;
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uint8_t level;
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} SMMUIOTLBKey;
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struct SMMUState {
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/* <private> */
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SysBusDevice dev;
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const char *mrtypename;
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MemoryRegion iomem;
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GHashTable *smmu_pcibus_by_busptr;
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GHashTable *configs; /* cache for configuration data */
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GHashTable *iotlb;
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SMMUPciBus *smmu_pcibus_by_bus_num[SMMU_PCI_BUS_MAX];
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PCIBus *pci_bus;
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QLIST_HEAD(, SMMUDevice) devices_with_notifiers;
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uint8_t bus_num;
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PCIBus *primary_bus;
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};
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struct SMMUBaseClass {
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/* <private> */
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SysBusDeviceClass parent_class;
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/*< public >*/
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DeviceRealize parent_realize;
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};
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#define TYPE_ARM_SMMU "arm-smmu"
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OBJECT_DECLARE_TYPE(SMMUState, SMMUBaseClass, ARM_SMMU)
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/* Return the SMMUPciBus handle associated to a PCI bus number */
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SMMUPciBus *smmu_find_smmu_pcibus(SMMUState *s, uint8_t bus_num);
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/* Return the stream ID of an SMMU device */
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static inline uint16_t smmu_get_sid(SMMUDevice *sdev)
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{
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return PCI_BUILD_BDF(pci_bus_num(sdev->bus), sdev->devfn);
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}
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/**
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* smmu_ptw - Perform the page table walk for a given iova / access flags
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* pair, according to @cfg translation config
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*/
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int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm,
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SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info);
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/**
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* select_tt - compute which translation table shall be used according to
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* the input iova and translation config and return the TT specific info
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*/
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SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova);
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/* Return the iommu mr associated to @sid, or NULL if none */
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IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t sid);
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#define SMMU_IOTLB_MAX_SIZE 256
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SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg,
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SMMUTransTableInfo *tt, hwaddr iova);
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void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *entry);
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SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t iova,
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uint8_t tg, uint8_t level);
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void smmu_iotlb_inv_all(SMMUState *s);
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void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid);
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void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
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uint8_t tg, uint64_t num_pages, uint8_t ttl);
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/* Unmap the range of all the notifiers registered to any IOMMU mr */
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void smmu_inv_notifiers_all(SMMUState *s);
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/* Unmap the range of all the notifiers registered to @mr */
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void smmu_inv_notifiers_mr(IOMMUMemoryRegion *mr);
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#endif /* HW_ARM_SMMU_COMMON_H */
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