These properties are part of the XICS API. They deserve to appear explicitely in the XICS header file. Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
573 lines
18 KiB
C
573 lines
18 KiB
C
/*
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* QEMU PowerPC PowerNV Processor Service Interface (PSI) model
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*
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* Copyright (c) 2015-2017, IBM Corporation.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "hw/hw.h"
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#include "target/ppc/cpu.h"
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#include "qemu/log.h"
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#include "qapi/error.h"
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#include "exec/address-spaces.h"
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#include "hw/ppc/fdt.h"
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#include "hw/ppc/pnv.h"
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#include "hw/ppc/pnv_xscom.h"
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#include "hw/ppc/pnv_psi.h"
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#include <libfdt.h>
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#define PSIHB_XSCOM_FIR_RW 0x00
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#define PSIHB_XSCOM_FIR_AND 0x01
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#define PSIHB_XSCOM_FIR_OR 0x02
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#define PSIHB_XSCOM_FIRMASK_RW 0x03
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#define PSIHB_XSCOM_FIRMASK_AND 0x04
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#define PSIHB_XSCOM_FIRMASK_OR 0x05
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#define PSIHB_XSCOM_FIRACT0 0x06
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#define PSIHB_XSCOM_FIRACT1 0x07
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/* Host Bridge Base Address Register */
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#define PSIHB_XSCOM_BAR 0x0a
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#define PSIHB_BAR_EN 0x0000000000000001ull
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/* FSP Base Address Register */
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#define PSIHB_XSCOM_FSPBAR 0x0b
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/* PSI Host Bridge Control/Status Register */
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#define PSIHB_XSCOM_CR 0x0e
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#define PSIHB_CR_FSP_CMD_ENABLE 0x8000000000000000ull
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#define PSIHB_CR_FSP_MMIO_ENABLE 0x4000000000000000ull
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#define PSIHB_CR_FSP_IRQ_ENABLE 0x1000000000000000ull
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#define PSIHB_CR_FSP_ERR_RSP_ENABLE 0x0800000000000000ull
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#define PSIHB_CR_PSI_LINK_ENABLE 0x0400000000000000ull
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#define PSIHB_CR_FSP_RESET 0x0200000000000000ull
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#define PSIHB_CR_PSIHB_RESET 0x0100000000000000ull
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#define PSIHB_CR_PSI_IRQ 0x0000800000000000ull
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#define PSIHB_CR_FSP_IRQ 0x0000400000000000ull
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#define PSIHB_CR_FSP_LINK_ACTIVE 0x0000200000000000ull
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#define PSIHB_CR_IRQ_CMD_EXPECT 0x0000010000000000ull
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/* and more ... */
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/* PSIHB Status / Error Mask Register */
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#define PSIHB_XSCOM_SEMR 0x0f
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/* XIVR, to signal interrupts to the CEC firmware. more XIVR below. */
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#define PSIHB_XSCOM_XIVR_FSP 0x10
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#define PSIHB_XIVR_SERVER_SH 40
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#define PSIHB_XIVR_SERVER_MSK (0xffffull << PSIHB_XIVR_SERVER_SH)
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#define PSIHB_XIVR_PRIO_SH 32
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#define PSIHB_XIVR_PRIO_MSK (0xffull << PSIHB_XIVR_PRIO_SH)
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#define PSIHB_XIVR_SRC_SH 29
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#define PSIHB_XIVR_SRC_MSK (0x7ull << PSIHB_XIVR_SRC_SH)
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#define PSIHB_XIVR_PENDING 0x01000000ull
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/* PSI Host Bridge Set Control/ Status Register */
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#define PSIHB_XSCOM_SCR 0x12
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/* PSI Host Bridge Clear Control/ Status Register */
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#define PSIHB_XSCOM_CCR 0x13
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/* DMA Upper Address Register */
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#define PSIHB_XSCOM_DMA_UPADD 0x14
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/* Interrupt Status */
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#define PSIHB_XSCOM_IRQ_STAT 0x15
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#define PSIHB_IRQ_STAT_OCC 0x0000001000000000ull
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#define PSIHB_IRQ_STAT_FSI 0x0000000800000000ull
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#define PSIHB_IRQ_STAT_LPCI2C 0x0000000400000000ull
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#define PSIHB_IRQ_STAT_LOCERR 0x0000000200000000ull
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#define PSIHB_IRQ_STAT_EXT 0x0000000100000000ull
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/* remaining XIVR */
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#define PSIHB_XSCOM_XIVR_OCC 0x16
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#define PSIHB_XSCOM_XIVR_FSI 0x17
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#define PSIHB_XSCOM_XIVR_LPCI2C 0x18
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#define PSIHB_XSCOM_XIVR_LOCERR 0x19
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#define PSIHB_XSCOM_XIVR_EXT 0x1a
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/* Interrupt Requester Source Compare Register */
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#define PSIHB_XSCOM_IRSN 0x1b
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#define PSIHB_IRSN_COMP_SH 45
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#define PSIHB_IRSN_COMP_MSK (0x7ffffull << PSIHB_IRSN_COMP_SH)
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#define PSIHB_IRSN_IRQ_MUX 0x0000000800000000ull
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#define PSIHB_IRSN_IRQ_RESET 0x0000000400000000ull
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#define PSIHB_IRSN_DOWNSTREAM_EN 0x0000000200000000ull
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#define PSIHB_IRSN_UPSTREAM_EN 0x0000000100000000ull
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#define PSIHB_IRSN_COMPMASK_SH 13
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#define PSIHB_IRSN_COMPMASK_MSK (0x7ffffull << PSIHB_IRSN_COMPMASK_SH)
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#define PSIHB_BAR_MASK 0x0003fffffff00000ull
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#define PSIHB_FSPBAR_MASK 0x0003ffff00000000ull
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static void pnv_psi_set_bar(PnvPsi *psi, uint64_t bar)
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{
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MemoryRegion *sysmem = get_system_memory();
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uint64_t old = psi->regs[PSIHB_XSCOM_BAR];
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psi->regs[PSIHB_XSCOM_BAR] = bar & (PSIHB_BAR_MASK | PSIHB_BAR_EN);
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/* Update MR, always remove it first */
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if (old & PSIHB_BAR_EN) {
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memory_region_del_subregion(sysmem, &psi->regs_mr);
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}
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/* Then add it back if needed */
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if (bar & PSIHB_BAR_EN) {
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uint64_t addr = bar & PSIHB_BAR_MASK;
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memory_region_add_subregion(sysmem, addr, &psi->regs_mr);
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}
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}
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static void pnv_psi_update_fsp_mr(PnvPsi *psi)
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{
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/* TODO: Update FSP MR if/when we support FSP BAR */
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}
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static void pnv_psi_set_cr(PnvPsi *psi, uint64_t cr)
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{
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uint64_t old = psi->regs[PSIHB_XSCOM_CR];
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psi->regs[PSIHB_XSCOM_CR] = cr;
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/* Check some bit changes */
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if ((old ^ psi->regs[PSIHB_XSCOM_CR]) & PSIHB_CR_FSP_MMIO_ENABLE) {
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pnv_psi_update_fsp_mr(psi);
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}
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}
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static void pnv_psi_set_irsn(PnvPsi *psi, uint64_t val)
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{
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ICSState *ics = &psi->ics;
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/* In this model we ignore the up/down enable bits for now
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* as SW doesn't use them (other than setting them at boot).
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* We ignore IRQ_MUX, its meaning isn't clear and we don't use
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* it and finally we ignore reset (XXX fix that ?)
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*/
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psi->regs[PSIHB_XSCOM_IRSN] = val & (PSIHB_IRSN_COMP_MSK |
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PSIHB_IRSN_IRQ_MUX |
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PSIHB_IRSN_IRQ_RESET |
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PSIHB_IRSN_DOWNSTREAM_EN |
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PSIHB_IRSN_UPSTREAM_EN);
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/* We ignore the compare mask as well, our ICS emulation is too
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* simplistic to make any use if it, and we extract the offset
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* from the compare value
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*/
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ics->offset = (val & PSIHB_IRSN_COMP_MSK) >> PSIHB_IRSN_COMP_SH;
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}
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/*
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* FSP and PSI interrupts are muxed under the same number.
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*/
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static const uint32_t xivr_regs[] = {
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[PSIHB_IRQ_PSI] = PSIHB_XSCOM_XIVR_FSP,
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[PSIHB_IRQ_FSP] = PSIHB_XSCOM_XIVR_FSP,
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[PSIHB_IRQ_OCC] = PSIHB_XSCOM_XIVR_OCC,
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[PSIHB_IRQ_FSI] = PSIHB_XSCOM_XIVR_FSI,
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[PSIHB_IRQ_LPC_I2C] = PSIHB_XSCOM_XIVR_LPCI2C,
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[PSIHB_IRQ_LOCAL_ERR] = PSIHB_XSCOM_XIVR_LOCERR,
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[PSIHB_IRQ_EXTERNAL] = PSIHB_XSCOM_XIVR_EXT,
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};
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static const uint32_t stat_regs[] = {
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[PSIHB_IRQ_PSI] = PSIHB_XSCOM_CR,
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[PSIHB_IRQ_FSP] = PSIHB_XSCOM_CR,
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[PSIHB_IRQ_OCC] = PSIHB_XSCOM_IRQ_STAT,
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[PSIHB_IRQ_FSI] = PSIHB_XSCOM_IRQ_STAT,
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[PSIHB_IRQ_LPC_I2C] = PSIHB_XSCOM_IRQ_STAT,
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[PSIHB_IRQ_LOCAL_ERR] = PSIHB_XSCOM_IRQ_STAT,
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[PSIHB_IRQ_EXTERNAL] = PSIHB_XSCOM_IRQ_STAT,
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};
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static const uint64_t stat_bits[] = {
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[PSIHB_IRQ_PSI] = PSIHB_CR_PSI_IRQ,
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[PSIHB_IRQ_FSP] = PSIHB_CR_FSP_IRQ,
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[PSIHB_IRQ_OCC] = PSIHB_IRQ_STAT_OCC,
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[PSIHB_IRQ_FSI] = PSIHB_IRQ_STAT_FSI,
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[PSIHB_IRQ_LPC_I2C] = PSIHB_IRQ_STAT_LPCI2C,
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[PSIHB_IRQ_LOCAL_ERR] = PSIHB_IRQ_STAT_LOCERR,
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[PSIHB_IRQ_EXTERNAL] = PSIHB_IRQ_STAT_EXT,
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};
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void pnv_psi_irq_set(PnvPsi *psi, PnvPsiIrq irq, bool state)
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{
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ICSState *ics = &psi->ics;
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uint32_t xivr_reg;
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uint32_t stat_reg;
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uint32_t src;
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bool masked;
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if (irq > PSIHB_IRQ_EXTERNAL) {
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qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", irq);
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return;
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}
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xivr_reg = xivr_regs[irq];
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stat_reg = stat_regs[irq];
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src = (psi->regs[xivr_reg] & PSIHB_XIVR_SRC_MSK) >> PSIHB_XIVR_SRC_SH;
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if (state) {
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psi->regs[stat_reg] |= stat_bits[irq];
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/* TODO: optimization, check mask here. That means
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* re-evaluating when unmasking
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*/
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qemu_irq_raise(ics->qirqs[src]);
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} else {
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psi->regs[stat_reg] &= ~stat_bits[irq];
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/* FSP and PSI are muxed so don't lower if either is still set */
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if (stat_reg != PSIHB_XSCOM_CR ||
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!(psi->regs[stat_reg] & (PSIHB_CR_PSI_IRQ | PSIHB_CR_FSP_IRQ))) {
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qemu_irq_lower(ics->qirqs[src]);
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} else {
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state = true;
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}
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}
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/* Note about the emulation of the pending bit: This isn't
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* entirely correct. The pending bit should be cleared when the
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* EOI has been received. However, we don't have callbacks on EOI
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* (especially not under KVM) so no way to emulate that properly,
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* so instead we just set that bit as the logical "output" of the
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* XIVR (ie pending & !masked)
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*
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* CLG: We could define a new ICS object with a custom eoi()
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* handler to clear the pending bit. But I am not sure this would
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* be useful for the software anyhow.
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*/
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masked = (psi->regs[xivr_reg] & PSIHB_XIVR_PRIO_MSK) == PSIHB_XIVR_PRIO_MSK;
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if (state && !masked) {
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psi->regs[xivr_reg] |= PSIHB_XIVR_PENDING;
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} else {
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psi->regs[xivr_reg] &= ~PSIHB_XIVR_PENDING;
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}
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}
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static void pnv_psi_set_xivr(PnvPsi *psi, uint32_t reg, uint64_t val)
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{
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ICSState *ics = &psi->ics;
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uint16_t server;
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uint8_t prio;
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uint8_t src;
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psi->regs[reg] = (psi->regs[reg] & PSIHB_XIVR_PENDING) |
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(val & (PSIHB_XIVR_SERVER_MSK |
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PSIHB_XIVR_PRIO_MSK |
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PSIHB_XIVR_SRC_MSK));
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val = psi->regs[reg];
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server = (val & PSIHB_XIVR_SERVER_MSK) >> PSIHB_XIVR_SERVER_SH;
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prio = (val & PSIHB_XIVR_PRIO_MSK) >> PSIHB_XIVR_PRIO_SH;
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src = (val & PSIHB_XIVR_SRC_MSK) >> PSIHB_XIVR_SRC_SH;
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if (src >= PSI_NUM_INTERRUPTS) {
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qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", src);
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return;
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}
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/* Remove pending bit if the IRQ is masked */
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if ((psi->regs[reg] & PSIHB_XIVR_PRIO_MSK) == PSIHB_XIVR_PRIO_MSK) {
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psi->regs[reg] &= ~PSIHB_XIVR_PENDING;
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}
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/* The low order 2 bits are the link pointer (Type II interrupts).
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* Shift back to get a valid IRQ server.
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*/
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server >>= 2;
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/* Now because of source remapping, weird things can happen
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* if you change the source number dynamically, our simple ICS
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* doesn't deal with remapping. So we just poke a different
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* ICS entry based on what source number was written. This will
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* do for now but a more accurate implementation would instead
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* use a fixed server/prio and a remapper of the generated irq.
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*/
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ics_simple_write_xive(ics, src, server, prio, prio);
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}
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static uint64_t pnv_psi_reg_read(PnvPsi *psi, uint32_t offset, bool mmio)
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{
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uint64_t val = 0xffffffffffffffffull;
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switch (offset) {
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case PSIHB_XSCOM_FIR_RW:
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case PSIHB_XSCOM_FIRACT0:
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case PSIHB_XSCOM_FIRACT1:
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case PSIHB_XSCOM_BAR:
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case PSIHB_XSCOM_FSPBAR:
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case PSIHB_XSCOM_CR:
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case PSIHB_XSCOM_XIVR_FSP:
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case PSIHB_XSCOM_XIVR_OCC:
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case PSIHB_XSCOM_XIVR_FSI:
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case PSIHB_XSCOM_XIVR_LPCI2C:
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case PSIHB_XSCOM_XIVR_LOCERR:
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case PSIHB_XSCOM_XIVR_EXT:
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case PSIHB_XSCOM_IRQ_STAT:
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case PSIHB_XSCOM_SEMR:
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case PSIHB_XSCOM_DMA_UPADD:
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case PSIHB_XSCOM_IRSN:
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val = psi->regs[offset];
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "PSI: read at Ox%" PRIx32 "\n", offset);
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}
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return val;
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}
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static void pnv_psi_reg_write(PnvPsi *psi, uint32_t offset, uint64_t val,
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bool mmio)
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{
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switch (offset) {
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case PSIHB_XSCOM_FIR_RW:
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case PSIHB_XSCOM_FIRACT0:
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case PSIHB_XSCOM_FIRACT1:
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case PSIHB_XSCOM_SEMR:
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case PSIHB_XSCOM_DMA_UPADD:
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psi->regs[offset] = val;
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break;
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case PSIHB_XSCOM_FIR_OR:
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psi->regs[PSIHB_XSCOM_FIR_RW] |= val;
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break;
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case PSIHB_XSCOM_FIR_AND:
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psi->regs[PSIHB_XSCOM_FIR_RW] &= val;
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break;
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case PSIHB_XSCOM_BAR:
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/* Only XSCOM can write this one */
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if (!mmio) {
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pnv_psi_set_bar(psi, val);
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} else {
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qemu_log_mask(LOG_GUEST_ERROR, "PSI: invalid write of BAR\n");
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}
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break;
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case PSIHB_XSCOM_FSPBAR:
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psi->regs[PSIHB_XSCOM_FSPBAR] = val & PSIHB_FSPBAR_MASK;
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pnv_psi_update_fsp_mr(psi);
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break;
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case PSIHB_XSCOM_CR:
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pnv_psi_set_cr(psi, val);
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break;
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case PSIHB_XSCOM_SCR:
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pnv_psi_set_cr(psi, psi->regs[PSIHB_XSCOM_CR] | val);
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break;
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case PSIHB_XSCOM_CCR:
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pnv_psi_set_cr(psi, psi->regs[PSIHB_XSCOM_CR] & ~val);
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break;
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case PSIHB_XSCOM_XIVR_FSP:
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case PSIHB_XSCOM_XIVR_OCC:
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case PSIHB_XSCOM_XIVR_FSI:
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case PSIHB_XSCOM_XIVR_LPCI2C:
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case PSIHB_XSCOM_XIVR_LOCERR:
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case PSIHB_XSCOM_XIVR_EXT:
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pnv_psi_set_xivr(psi, offset, val);
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break;
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case PSIHB_XSCOM_IRQ_STAT:
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/* Read only */
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qemu_log_mask(LOG_GUEST_ERROR, "PSI: invalid write of IRQ_STAT\n");
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break;
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case PSIHB_XSCOM_IRSN:
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pnv_psi_set_irsn(psi, val);
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "PSI: write at Ox%" PRIx32 "\n", offset);
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}
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}
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/*
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* The values of the registers when accessed through the MMIO region
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* follow the relation : xscom = (mmio + 0x50) >> 3
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*/
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static uint64_t pnv_psi_mmio_read(void *opaque, hwaddr addr, unsigned size)
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{
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return pnv_psi_reg_read(opaque, (addr >> 3) + PSIHB_XSCOM_BAR, true);
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}
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static void pnv_psi_mmio_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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pnv_psi_reg_write(opaque, (addr >> 3) + PSIHB_XSCOM_BAR, val, true);
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}
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static const MemoryRegionOps psi_mmio_ops = {
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.read = pnv_psi_mmio_read,
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.write = pnv_psi_mmio_write,
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.endianness = DEVICE_BIG_ENDIAN,
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.valid = {
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|
.min_access_size = 8,
|
|
.max_access_size = 8,
|
|
},
|
|
.impl = {
|
|
.min_access_size = 8,
|
|
.max_access_size = 8,
|
|
},
|
|
};
|
|
|
|
static uint64_t pnv_psi_xscom_read(void *opaque, hwaddr addr, unsigned size)
|
|
{
|
|
return pnv_psi_reg_read(opaque, addr >> 3, false);
|
|
}
|
|
|
|
static void pnv_psi_xscom_write(void *opaque, hwaddr addr,
|
|
uint64_t val, unsigned size)
|
|
{
|
|
pnv_psi_reg_write(opaque, addr >> 3, val, false);
|
|
}
|
|
|
|
static const MemoryRegionOps pnv_psi_xscom_ops = {
|
|
.read = pnv_psi_xscom_read,
|
|
.write = pnv_psi_xscom_write,
|
|
.endianness = DEVICE_BIG_ENDIAN,
|
|
.valid = {
|
|
.min_access_size = 8,
|
|
.max_access_size = 8,
|
|
},
|
|
.impl = {
|
|
.min_access_size = 8,
|
|
.max_access_size = 8,
|
|
}
|
|
};
|
|
|
|
static void pnv_psi_init(Object *obj)
|
|
{
|
|
PnvPsi *psi = PNV_PSI(obj);
|
|
|
|
object_initialize(&psi->ics, sizeof(psi->ics), TYPE_ICS_SIMPLE);
|
|
object_property_add_child(obj, "ics-psi", OBJECT(&psi->ics), NULL);
|
|
}
|
|
|
|
static const uint8_t irq_to_xivr[] = {
|
|
PSIHB_XSCOM_XIVR_FSP,
|
|
PSIHB_XSCOM_XIVR_OCC,
|
|
PSIHB_XSCOM_XIVR_FSI,
|
|
PSIHB_XSCOM_XIVR_LPCI2C,
|
|
PSIHB_XSCOM_XIVR_LOCERR,
|
|
PSIHB_XSCOM_XIVR_EXT,
|
|
};
|
|
|
|
static void pnv_psi_realize(DeviceState *dev, Error **errp)
|
|
{
|
|
PnvPsi *psi = PNV_PSI(dev);
|
|
ICSState *ics = &psi->ics;
|
|
Object *obj;
|
|
Error *err = NULL;
|
|
unsigned int i;
|
|
|
|
obj = object_property_get_link(OBJECT(dev), "xics", &err);
|
|
if (!obj) {
|
|
error_setg(errp, "%s: required link 'xics' not found: %s",
|
|
__func__, error_get_pretty(err));
|
|
return;
|
|
}
|
|
|
|
/* Create PSI interrupt control source */
|
|
object_property_add_const_link(OBJECT(ics), ICS_PROP_XICS, obj,
|
|
&error_abort);
|
|
object_property_set_int(OBJECT(ics), PSI_NUM_INTERRUPTS, "nr-irqs", &err);
|
|
if (err) {
|
|
error_propagate(errp, err);
|
|
return;
|
|
}
|
|
object_property_set_bool(OBJECT(ics), true, "realized", &err);
|
|
if (err) {
|
|
error_propagate(errp, err);
|
|
return;
|
|
}
|
|
|
|
for (i = 0; i < ics->nr_irqs; i++) {
|
|
ics_set_irq_type(ics, i, true);
|
|
}
|
|
|
|
/* XSCOM region for PSI registers */
|
|
pnv_xscom_region_init(&psi->xscom_regs, OBJECT(dev), &pnv_psi_xscom_ops,
|
|
psi, "xscom-psi", PNV_XSCOM_PSIHB_SIZE);
|
|
|
|
/* Initialize MMIO region */
|
|
memory_region_init_io(&psi->regs_mr, OBJECT(dev), &psi_mmio_ops, psi,
|
|
"psihb", PNV_PSIHB_SIZE);
|
|
|
|
/* Default BAR for MMIO region */
|
|
pnv_psi_set_bar(psi, psi->bar | PSIHB_BAR_EN);
|
|
|
|
/* Default sources in XIVR */
|
|
for (i = 0; i < PSI_NUM_INTERRUPTS; i++) {
|
|
uint8_t xivr = irq_to_xivr[i];
|
|
psi->regs[xivr] = PSIHB_XIVR_PRIO_MSK |
|
|
((uint64_t) i << PSIHB_XIVR_SRC_SH);
|
|
}
|
|
}
|
|
|
|
static int pnv_psi_populate(PnvXScomInterface *dev, void *fdt, int xscom_offset)
|
|
{
|
|
const char compat[] = "ibm,power8-psihb-x\0ibm,psihb-x";
|
|
char *name;
|
|
int offset;
|
|
uint32_t lpc_pcba = PNV_XSCOM_PSIHB_BASE;
|
|
uint32_t reg[] = {
|
|
cpu_to_be32(lpc_pcba),
|
|
cpu_to_be32(PNV_XSCOM_PSIHB_SIZE)
|
|
};
|
|
|
|
name = g_strdup_printf("psihb@%x", lpc_pcba);
|
|
offset = fdt_add_subnode(fdt, xscom_offset, name);
|
|
_FDT(offset);
|
|
g_free(name);
|
|
|
|
_FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))));
|
|
|
|
_FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 2)));
|
|
_FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 1)));
|
|
_FDT((fdt_setprop(fdt, offset, "compatible", compat,
|
|
sizeof(compat))));
|
|
return 0;
|
|
}
|
|
|
|
static Property pnv_psi_properties[] = {
|
|
DEFINE_PROP_UINT64("bar", PnvPsi, bar, 0),
|
|
DEFINE_PROP_UINT64("fsp-bar", PnvPsi, fsp_bar, 0),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void pnv_psi_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass);
|
|
|
|
xdc->populate = pnv_psi_populate;
|
|
|
|
dc->realize = pnv_psi_realize;
|
|
dc->props = pnv_psi_properties;
|
|
}
|
|
|
|
static const TypeInfo pnv_psi_info = {
|
|
.name = TYPE_PNV_PSI,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(PnvPsi),
|
|
.instance_init = pnv_psi_init,
|
|
.class_init = pnv_psi_class_init,
|
|
.interfaces = (InterfaceInfo[]) {
|
|
{ TYPE_PNV_XSCOM_INTERFACE },
|
|
{ }
|
|
}
|
|
};
|
|
|
|
static void pnv_psi_register_types(void)
|
|
{
|
|
type_register_static(&pnv_psi_info);
|
|
}
|
|
|
|
type_init(pnv_psi_register_types)
|