When a subchannel becomes pending with unit exception, start pending (and for that matter, halt or clear pending) are not removed in the actl. Device active and subchannel active, however, are (due to the subchannel becoming status pending with primary respectively secondary status). The other conditions in the actl are only cleared when the guest executes tsch on the subchannel. Signed-off-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Matthew Rosato <mjrosato@linux.ibm.com> Tested-by: Jared Rossi <jrossi@linux.ibm.com> Message-Id: <20210705163952.736020-3-cohuck@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
337 lines
11 KiB
C
337 lines
11 KiB
C
/*
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* Channel subsystem structures and definitions.
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*
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* Copyright 2012 IBM Corp.
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* Author(s): Cornelia Huck <cornelia.huck@de.ibm.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or (at
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* your option) any later version. See the COPYING file in the top-level
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* directory.
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*/
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#ifndef CSS_H
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#define CSS_H
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#include "hw/s390x/adapter.h"
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#include "hw/s390x/s390_flic.h"
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#include "hw/s390x/ioinst.h"
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#include "sysemu/kvm.h"
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#include "target/s390x/cpu-qom.h"
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/* Channel subsystem constants. */
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#define MAX_DEVNO 65535
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#define MAX_SCHID 65535
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#define MAX_SSID 3
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#define MAX_CSSID 255
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#define MAX_CHPID 255
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#define MAX_ISC 7
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#define MAX_CIWS 62
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#define VIRTUAL_CSSID 0xfe
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#define VIRTIO_CCW_CHPID 0 /* used by convention */
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typedef struct CIW {
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uint8_t type;
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uint8_t command;
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uint16_t count;
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} QEMU_PACKED CIW;
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typedef struct SenseId {
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/* common part */
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uint8_t reserved; /* always 0x'FF' */
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uint16_t cu_type; /* control unit type */
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uint8_t cu_model; /* control unit model */
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uint16_t dev_type; /* device type */
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uint8_t dev_model; /* device model */
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uint8_t unused; /* padding byte */
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/* extended part */
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CIW ciw[MAX_CIWS]; /* variable # of CIWs */
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} SenseId; /* Note: No QEMU_PACKED due to unaligned members */
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/* Channel measurements, from linux/drivers/s390/cio/cmf.c. */
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typedef struct CMB {
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uint16_t ssch_rsch_count;
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uint16_t sample_count;
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uint32_t device_connect_time;
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uint32_t function_pending_time;
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uint32_t device_disconnect_time;
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uint32_t control_unit_queuing_time;
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uint32_t device_active_only_time;
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uint32_t reserved[2];
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} QEMU_PACKED CMB;
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typedef struct CMBE {
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uint32_t ssch_rsch_count;
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uint32_t sample_count;
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uint32_t device_connect_time;
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uint32_t function_pending_time;
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uint32_t device_disconnect_time;
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uint32_t control_unit_queuing_time;
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uint32_t device_active_only_time;
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uint32_t device_busy_time;
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uint32_t initial_command_response_time;
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uint32_t reserved[7];
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} QEMU_PACKED CMBE;
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typedef enum CcwDataStreamOp {
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CDS_OP_R = 0, /* read, false when used as is_write */
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CDS_OP_W = 1, /* write, true when used as is_write */
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CDS_OP_A = 2 /* advance, should not be used as is_write */
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} CcwDataStreamOp;
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/* normal usage is via SuchchDev.cds instead of instantiating */
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typedef struct CcwDataStream {
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#define CDS_F_IDA 0x01
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#define CDS_F_MIDA 0x02
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#define CDS_F_I2K 0x04
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#define CDS_F_C64 0x08
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#define CDS_F_FMT 0x10 /* CCW format-1 */
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#define CDS_F_STREAM_BROKEN 0x80
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uint8_t flags;
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uint8_t at_idaw;
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uint16_t at_byte;
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uint16_t count;
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uint32_t cda_orig;
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int (*op_handler)(struct CcwDataStream *cds, void *buff, int len,
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CcwDataStreamOp op);
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hwaddr cda;
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bool do_skip;
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} CcwDataStream;
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/*
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* IO instructions conclude according to this. Currently we have only
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* cc codes. Valid values are 0, 1, 2, 3 and the generic semantic for
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* IO instructions is described briefly. For more details consult the PoP.
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*/
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typedef enum IOInstEnding {
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/* produced expected result */
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IOINST_CC_EXPECTED = 0,
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/* status conditions were present or produced alternate result */
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IOINST_CC_STATUS_PRESENT = 1,
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/* inst. ineffective because busy with previously initiated function */
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IOINST_CC_BUSY = 2,
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/* inst. ineffective because not operational */
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IOINST_CC_NOT_OPERATIONAL = 3
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} IOInstEnding;
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typedef struct SubchDev SubchDev;
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struct SubchDev {
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/* channel-subsystem related things: */
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SCHIB curr_status; /* Needs alignment and thus must come first */
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ORB orb;
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uint8_t cssid;
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uint8_t ssid;
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uint16_t schid;
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uint16_t devno;
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uint8_t sense_data[32];
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hwaddr channel_prog;
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CCW1 last_cmd;
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bool last_cmd_valid;
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bool ccw_fmt_1;
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bool thinint_active;
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uint8_t ccw_no_data_cnt;
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uint16_t migrated_schid; /* used for mismatch detection */
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CcwDataStream cds;
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/* transport-provided data: */
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int (*ccw_cb) (SubchDev *, CCW1);
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void (*disable_cb)(SubchDev *);
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IOInstEnding (*do_subchannel_work) (SubchDev *);
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void (*irb_cb)(SubchDev *, IRB *);
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SenseId id;
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void *driver_data;
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ESW esw;
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};
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static inline void sch_gen_unit_exception(SubchDev *sch)
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{
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sch->curr_status.scsw.ctrl &= ~(SCSW_ACTL_DEVICE_ACTIVE |
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SCSW_ACTL_SUBCH_ACTIVE);
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sch->curr_status.scsw.ctrl |= SCSW_STCTL_PRIMARY |
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SCSW_STCTL_SECONDARY |
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SCSW_STCTL_ALERT |
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SCSW_STCTL_STATUS_PEND;
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sch->curr_status.scsw.cpa = sch->channel_prog + 8;
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sch->curr_status.scsw.dstat = SCSW_DSTAT_UNIT_EXCEP;
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}
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extern const VMStateDescription vmstate_subch_dev;
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/*
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* Identify a device within the channel subsystem.
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* Note that this can be used to identify either the subchannel or
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* the attached I/O device, as there's always one I/O device per
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* subchannel.
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*/
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typedef struct CssDevId {
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uint8_t cssid;
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uint8_t ssid;
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uint16_t devid;
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bool valid;
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} CssDevId;
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extern const PropertyInfo css_devid_propinfo;
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#define DEFINE_PROP_CSS_DEV_ID(_n, _s, _f) \
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DEFINE_PROP(_n, _s, _f, css_devid_propinfo, CssDevId)
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typedef struct IndAddr {
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hwaddr addr;
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uint64_t map;
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unsigned long refcnt;
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int32_t len;
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QTAILQ_ENTRY(IndAddr) sibling;
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} IndAddr;
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extern const VMStateDescription vmstate_ind_addr;
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#define VMSTATE_PTR_TO_IND_ADDR(_f, _s) \
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VMSTATE_STRUCT(_f, _s, 1, vmstate_ind_addr, IndAddr*)
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IndAddr *get_indicator(hwaddr ind_addr, int len);
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void release_indicator(AdapterInfo *adapter, IndAddr *indicator);
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int map_indicator(AdapterInfo *adapter, IndAddr *indicator);
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typedef SubchDev *(*css_subch_cb_func)(uint8_t m, uint8_t cssid, uint8_t ssid,
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uint16_t schid);
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int css_create_css_image(uint8_t cssid, bool default_image);
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bool css_devno_used(uint8_t cssid, uint8_t ssid, uint16_t devno);
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void css_subch_assign(uint8_t cssid, uint8_t ssid, uint16_t schid,
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uint16_t devno, SubchDev *sch);
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void css_sch_build_virtual_schib(SubchDev *sch, uint8_t chpid, uint8_t type);
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int css_sch_build_schib(SubchDev *sch, CssDevId *dev_id);
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unsigned int css_find_free_chpid(uint8_t cssid);
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uint16_t css_build_subchannel_id(SubchDev *sch);
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void copy_scsw_to_guest(SCSW *dest, const SCSW *src);
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void copy_esw_to_guest(ESW *dest, const ESW *src);
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void css_inject_io_interrupt(SubchDev *sch);
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void css_reset(void);
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void css_reset_sch(SubchDev *sch);
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void css_crw_add_to_queue(CRW crw);
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void css_queue_crw(uint8_t rsc, uint8_t erc, int solicited,
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int chain, uint16_t rsid);
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void css_generate_sch_crws(uint8_t cssid, uint8_t ssid, uint16_t schid,
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int hotplugged, int add);
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void css_generate_chp_crws(uint8_t cssid, uint8_t chpid);
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void css_generate_css_crws(uint8_t cssid);
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void css_clear_sei_pending(void);
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IOInstEnding s390_ccw_cmd_request(SubchDev *sch);
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IOInstEnding do_subchannel_work_virtual(SubchDev *sub);
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IOInstEnding do_subchannel_work_passthrough(SubchDev *sub);
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void build_irb_passthrough(SubchDev *sch, IRB *irb);
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void build_irb_virtual(SubchDev *sch, IRB *irb);
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int s390_ccw_halt(SubchDev *sch);
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int s390_ccw_clear(SubchDev *sch);
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IOInstEnding s390_ccw_store(SubchDev *sch);
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typedef enum {
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CSS_IO_ADAPTER_VIRTIO = 0,
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CSS_IO_ADAPTER_PCI = 1,
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CSS_IO_ADAPTER_TYPE_NUMS,
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} CssIoAdapterType;
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void css_adapter_interrupt(CssIoAdapterType type, uint8_t isc);
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int css_do_sic(CPUS390XState *env, uint8_t isc, uint16_t mode);
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uint32_t css_get_adapter_id(CssIoAdapterType type, uint8_t isc);
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void css_register_io_adapters(CssIoAdapterType type, bool swap, bool maskable,
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uint8_t flags, Error **errp);
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#ifndef CONFIG_USER_ONLY
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SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
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uint16_t schid);
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bool css_subch_visible(SubchDev *sch);
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void css_conditional_io_interrupt(SubchDev *sch);
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IOInstEnding css_do_stsch(SubchDev *sch, SCHIB *schib);
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bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid);
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IOInstEnding css_do_msch(SubchDev *sch, const SCHIB *schib);
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IOInstEnding css_do_xsch(SubchDev *sch);
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IOInstEnding css_do_csch(SubchDev *sch);
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IOInstEnding css_do_hsch(SubchDev *sch);
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IOInstEnding css_do_ssch(SubchDev *sch, ORB *orb);
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int css_do_tsch_get_irb(SubchDev *sch, IRB *irb, int *irb_len);
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void css_do_tsch_update_subch(SubchDev *sch);
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int css_do_stcrw(CRW *crw);
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void css_undo_stcrw(CRW *crw);
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int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid,
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int rfmt, void *buf);
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void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo);
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int css_enable_mcsse(void);
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int css_enable_mss(void);
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IOInstEnding css_do_rsch(SubchDev *sch);
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int css_do_rchp(uint8_t cssid, uint8_t chpid);
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bool css_present(uint8_t cssid);
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#endif
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extern const PropertyInfo css_devid_ro_propinfo;
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#define DEFINE_PROP_CSS_DEV_ID_RO(_n, _s, _f) \
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DEFINE_PROP(_n, _s, _f, css_devid_ro_propinfo, CssDevId)
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/**
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* Create a subchannel for the given bus id.
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*
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* If @p bus_id is valid, verify that it is not already in use, and find a
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* free devno for it.
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* If @p bus_id is not valid find a free subchannel id and device number
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* across all subchannel sets and all css images starting from the default
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* css image.
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*
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* If either of the former actions succeed, allocate a subchannel structure,
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* initialise it with the bus id, subchannel id and device number, register
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* it with the CSS and return it. Otherwise return NULL.
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*
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* The caller becomes owner of the returned subchannel structure and
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* is responsible for unregistering and freeing it.
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*/
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SubchDev *css_create_sch(CssDevId bus_id, Error **errp);
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/** Turn on css migration */
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void css_register_vmstate(void);
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void ccw_dstream_init(CcwDataStream *cds, CCW1 const *ccw, ORB const *orb);
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static inline void ccw_dstream_rewind(CcwDataStream *cds)
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{
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cds->at_byte = 0;
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cds->at_idaw = 0;
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cds->cda = cds->cda_orig;
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}
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static inline bool ccw_dstream_good(CcwDataStream *cds)
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{
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return !(cds->flags & CDS_F_STREAM_BROKEN);
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}
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static inline uint16_t ccw_dstream_residual_count(CcwDataStream *cds)
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{
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return cds->count - cds->at_byte;
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}
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static inline uint16_t ccw_dstream_avail(CcwDataStream *cds)
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{
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return ccw_dstream_good(cds) ? ccw_dstream_residual_count(cds) : 0;
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}
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static inline int ccw_dstream_advance(CcwDataStream *cds, int len)
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{
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return cds->op_handler(cds, NULL, len, CDS_OP_A);
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}
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static inline int ccw_dstream_write_buf(CcwDataStream *cds, void *buff, int len)
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{
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return cds->op_handler(cds, buff, len, CDS_OP_W);
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}
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static inline int ccw_dstream_read_buf(CcwDataStream *cds, void *buff, int len)
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{
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return cds->op_handler(cds, buff, len, CDS_OP_R);
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}
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#define ccw_dstream_read(cds, v) ccw_dstream_read_buf((cds), &(v), sizeof(v))
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#define ccw_dstream_write(cds, v) ccw_dstream_write_buf((cds), &(v), sizeof(v))
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#endif
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