qemu-patch-raspberry4/target
Richard Henderson 5d23d53023 target/s390x: move tcg_gen_insn_start to s390x_tr_insn_start
We use INDEX_op_insn_start to make the start of instruction boundaries.
If we don't do it in the .insn_start hook things get confused especially
now plugins want to use that marking to identify the start of instructions
and will bomb out if it sees instrumented ops before the first instruction
boundary.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20211011185332.166763-1-richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2021-10-12 08:37:53 +01:00
..
alpha hw/core: Make do_unaligned_access noreturn 2021-09-21 19:36:44 -07:00
arm tcg: Rename TCGMemOpIdx to MemOpIdx 2021-10-05 16:53:17 -07:00
avr include/exec: Move cpu_signal_handler declaration 2021-09-21 19:36:44 -07:00
cris include/exec: Move cpu_signal_handler declaration 2021-09-21 19:36:44 -07:00
hexagon target/hexagon: Use tcg_constant_* 2021-10-06 10:29:56 -05:00
hppa hw/core: Make do_unaligned_access noreturn 2021-09-21 19:36:44 -07:00
i386 tcg: Rename TCGMemOpIdx to MemOpIdx 2021-10-05 16:53:17 -07:00
m68k tcg: Rename TCGMemOpIdx to MemOpIdx 2021-10-05 16:53:17 -07:00
microblaze hw/core: Make do_unaligned_access noreturn 2021-09-21 19:36:44 -07:00
mips tcg: Rename TCGMemOpIdx to MemOpIdx 2021-10-05 16:53:17 -07:00
nios2 hw/core: Make do_unaligned_access noreturn 2021-09-21 19:36:44 -07:00
openrisc include/exec: Move cpu_signal_handler declaration 2021-09-21 19:36:44 -07:00
ppc target/ppc: Check privilege level based on PSR and LPCR[HR] in tlbie[l] 2021-09-30 12:26:06 +10:00
riscv target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty() 2021-10-07 08:41:33 +10:00
rx include/exec: Move cpu_signal_handler declaration 2021-09-21 19:36:44 -07:00
s390x target/s390x: move tcg_gen_insn_start to s390x_tr_insn_start 2021-10-12 08:37:53 +01:00
sh4 target/sh4: Use lookup_symbol in sh4_tr_disas_log 2021-10-04 09:47:26 +02:00
sparc tcg: Rename TCGMemOpIdx to MemOpIdx 2021-10-05 16:53:17 -07:00
tricore include/exec: Move cpu_signal_handler declaration 2021-09-21 19:36:44 -07:00
xtensa target/xtensa: list cores in a text file 2021-10-05 13:10:29 +02:00
Kconfig meson: Introduce target-specific Kconfig 2021-07-09 18:21:34 +02:00
meson.build Drop the deprecated unicore32 target 2021-05-12 18:20:52 +02:00