Add a flag to MIPSCPUClass in order to avoid needing to replace mips_tcg_ops.do_transaction_failed. Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20210227232519.222663-2-richard.henderson@linaro.org>
422 lines
12 KiB
C
422 lines
12 KiB
C
/*
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* MIPS emulation helpers for qemu.
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*
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* Copyright (c) 2004-2005 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "internal.h"
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#include "exec/helper-proto.h"
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#include "exec/exec-all.h"
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#include "exec/memop.h"
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#include "fpu_helper.h"
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/* 64 bits arithmetic for 32 bits hosts */
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static inline uint64_t get_HILO(CPUMIPSState *env)
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{
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return ((uint64_t)(env->active_tc.HI[0]) << 32) |
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(uint32_t)env->active_tc.LO[0];
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}
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static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)
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{
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env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
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return env->active_tc.HI[0] = (int32_t)(HILO >> 32);
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}
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static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO)
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{
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target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
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env->active_tc.HI[0] = (int32_t)(HILO >> 32);
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return tmp;
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}
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/* Multiplication variants of the vr54xx. */
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target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,
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target_ulong arg2)
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{
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return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 *
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(int64_t)(int32_t)arg2));
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}
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target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,
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target_ulong arg2)
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{
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return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 *
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(uint64_t)(uint32_t)arg2);
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}
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target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,
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target_ulong arg2)
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{
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return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
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(int64_t)(int32_t)arg2);
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}
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target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,
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target_ulong arg2)
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{
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return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
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(int64_t)(int32_t)arg2);
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}
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target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,
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target_ulong arg2)
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{
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return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
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(uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
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}
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target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,
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target_ulong arg2)
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{
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return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
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(uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
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}
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target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,
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target_ulong arg2)
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{
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return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
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(int64_t)(int32_t)arg2);
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}
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target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,
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target_ulong arg2)
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{
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return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
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(int64_t)(int32_t)arg2);
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}
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target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,
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target_ulong arg2)
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{
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return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
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(uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
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}
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target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,
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target_ulong arg2)
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{
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return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
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(uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
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}
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target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,
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target_ulong arg2)
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{
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return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
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}
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target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,
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target_ulong arg2)
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{
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return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
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(uint64_t)(uint32_t)arg2);
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}
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target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,
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target_ulong arg2)
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{
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return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 *
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(int64_t)(int32_t)arg2);
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}
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target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
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target_ulong arg2)
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{
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return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 *
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(uint64_t)(uint32_t)arg2);
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}
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static inline target_ulong bitswap(target_ulong v)
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{
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v = ((v >> 1) & (target_ulong)0x5555555555555555ULL) |
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((v & (target_ulong)0x5555555555555555ULL) << 1);
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v = ((v >> 2) & (target_ulong)0x3333333333333333ULL) |
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((v & (target_ulong)0x3333333333333333ULL) << 2);
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v = ((v >> 4) & (target_ulong)0x0F0F0F0F0F0F0F0FULL) |
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((v & (target_ulong)0x0F0F0F0F0F0F0F0FULL) << 4);
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return v;
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}
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#ifdef TARGET_MIPS64
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target_ulong helper_dbitswap(target_ulong rt)
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{
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return bitswap(rt);
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}
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#endif
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target_ulong helper_bitswap(target_ulong rt)
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{
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return (int32_t)bitswap(rt);
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}
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target_ulong helper_rotx(target_ulong rs, uint32_t shift, uint32_t shiftx,
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uint32_t stripe)
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{
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int i;
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uint64_t tmp0 = ((uint64_t)rs) << 32 | ((uint64_t)rs & 0xffffffff);
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uint64_t tmp1 = tmp0;
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for (i = 0; i <= 46; i++) {
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int s;
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if (i & 0x8) {
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s = shift;
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} else {
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s = shiftx;
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}
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if (stripe != 0 && !(i & 0x4)) {
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s = ~s;
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}
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if (s & 0x10) {
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if (tmp0 & (1LL << (i + 16))) {
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tmp1 |= 1LL << i;
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} else {
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tmp1 &= ~(1LL << i);
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}
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}
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}
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uint64_t tmp2 = tmp1;
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for (i = 0; i <= 38; i++) {
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int s;
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if (i & 0x4) {
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s = shift;
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} else {
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s = shiftx;
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}
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if (s & 0x8) {
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if (tmp1 & (1LL << (i + 8))) {
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tmp2 |= 1LL << i;
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} else {
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tmp2 &= ~(1LL << i);
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}
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}
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}
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uint64_t tmp3 = tmp2;
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for (i = 0; i <= 34; i++) {
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int s;
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if (i & 0x2) {
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s = shift;
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} else {
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s = shiftx;
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}
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if (s & 0x4) {
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if (tmp2 & (1LL << (i + 4))) {
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tmp3 |= 1LL << i;
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} else {
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tmp3 &= ~(1LL << i);
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}
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}
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}
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uint64_t tmp4 = tmp3;
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for (i = 0; i <= 32; i++) {
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int s;
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if (i & 0x1) {
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s = shift;
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} else {
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s = shiftx;
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}
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if (s & 0x2) {
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if (tmp3 & (1LL << (i + 2))) {
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tmp4 |= 1LL << i;
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} else {
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tmp4 &= ~(1LL << i);
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}
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}
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}
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uint64_t tmp5 = tmp4;
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for (i = 0; i <= 31; i++) {
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int s;
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s = shift;
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if (s & 0x1) {
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if (tmp4 & (1LL << (i + 1))) {
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tmp5 |= 1LL << i;
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} else {
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tmp5 &= ~(1LL << i);
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}
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}
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}
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return (int64_t)(int32_t)(uint32_t)tmp5;
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}
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void helper_fork(target_ulong arg1, target_ulong arg2)
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{
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/*
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* arg1 = rt, arg2 = rs
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* TODO: store to TC register
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*/
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}
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target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
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{
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target_long arg1 = arg;
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if (arg1 < 0) {
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/* No scheduling policy implemented. */
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if (arg1 != -2) {
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if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
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env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
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env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
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env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
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do_raise_exception(env, EXCP_THREAD, GETPC());
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}
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}
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} else if (arg1 == 0) {
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if (0) {
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/* TODO: TC underflow */
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env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
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do_raise_exception(env, EXCP_THREAD, GETPC());
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} else {
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/* TODO: Deallocate TC */
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}
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} else if (arg1 > 0) {
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/* Yield qualifier inputs not implemented. */
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env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
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env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
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do_raise_exception(env, EXCP_THREAD, GETPC());
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}
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return env->CP0_YQMask;
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}
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static inline void check_hwrena(CPUMIPSState *env, int reg, uintptr_t pc)
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{
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if ((env->hflags & MIPS_HFLAG_CP0) || (env->CP0_HWREna & (1 << reg))) {
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return;
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}
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do_raise_exception(env, EXCP_RI, pc);
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}
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target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
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{
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check_hwrena(env, 0, GETPC());
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return env->CP0_EBase & 0x3ff;
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}
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target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
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{
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check_hwrena(env, 1, GETPC());
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return env->SYNCI_Step;
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}
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target_ulong helper_rdhwr_cc(CPUMIPSState *env)
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{
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check_hwrena(env, 2, GETPC());
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#ifdef CONFIG_USER_ONLY
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return env->CP0_Count;
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#else
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return (int32_t)cpu_mips_get_count(env);
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#endif
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}
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target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
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{
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check_hwrena(env, 3, GETPC());
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return env->CCRes;
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}
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target_ulong helper_rdhwr_performance(CPUMIPSState *env)
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{
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check_hwrena(env, 4, GETPC());
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return env->CP0_Performance0;
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}
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target_ulong helper_rdhwr_xnp(CPUMIPSState *env)
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{
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check_hwrena(env, 5, GETPC());
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return (env->CP0_Config5 >> CP0C5_XNP) & 1;
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}
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void helper_pmon(CPUMIPSState *env, int function)
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{
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function /= 2;
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switch (function) {
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case 2: /* TODO: char inbyte(int waitflag); */
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if (env->active_tc.gpr[4] == 0) {
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env->active_tc.gpr[2] = -1;
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}
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/* Fall through */
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case 11: /* TODO: char inbyte (void); */
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env->active_tc.gpr[2] = -1;
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break;
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case 3:
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case 12:
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printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
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break;
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case 17:
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break;
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case 158:
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{
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unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4];
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printf("%s", fmt);
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}
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break;
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}
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}
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#if !defined(CONFIG_USER_ONLY)
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void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
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MMUAccessType access_type,
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int mmu_idx, uintptr_t retaddr)
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{
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MIPSCPU *cpu = MIPS_CPU(cs);
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CPUMIPSState *env = &cpu->env;
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int error_code = 0;
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int excp;
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if (!(env->hflags & MIPS_HFLAG_DM)) {
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env->CP0_BadVAddr = addr;
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}
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if (access_type == MMU_DATA_STORE) {
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excp = EXCP_AdES;
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} else {
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excp = EXCP_AdEL;
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if (access_type == MMU_INST_FETCH) {
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error_code |= EXCP_INST_NOTAVAIL;
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}
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}
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do_raise_exception_err(env, excp, error_code, retaddr);
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}
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void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
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vaddr addr, unsigned size,
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MMUAccessType access_type,
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int mmu_idx, MemTxAttrs attrs,
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MemTxResult response, uintptr_t retaddr)
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{
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MIPSCPU *cpu = MIPS_CPU(cs);
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MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
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CPUMIPSState *env = &cpu->env;
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if (access_type == MMU_INST_FETCH) {
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do_raise_exception(env, EXCP_IBE, retaddr);
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} else if (!mcc->no_data_aborts) {
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do_raise_exception(env, EXCP_DBE, retaddr);
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}
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}
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#endif /* !CONFIG_USER_ONLY */
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