a2b0a27d33
To ease maintenance, move all TCG specific files under the tcg/ sub-directory. Adapt the Meson machinery. The following prototypes: - mips_tcg_init() - mips_cpu_do_unaligned_access() - mips_cpu_do_transaction_failed() can now be restricted to the "tcg-internal.h" header. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-29-f4bug@amsat.org>
44 lines
966 B
C
44 lines
966 B
C
/*
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* MIPS emulation for QEMU - Release 6 translation routines
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*
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* Copyright (c) 2020 Philippe Mathieu-Daudé
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*
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* SPDX-License-Identifier: LGPL-2.1-or-later
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*
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* This code is licensed under the LGPL v2.1 or later.
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*/
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#include "qemu/osdep.h"
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#include "tcg/tcg-op.h"
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#include "exec/helper-gen.h"
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#include "translate.h"
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/* Include the auto-generated decoder. */
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#include "decode-mips32r6.c.inc"
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#include "decode-mips64r6.c.inc"
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bool trans_REMOVED(DisasContext *ctx, arg_REMOVED *a)
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{
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gen_reserved_instruction(ctx);
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return true;
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}
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static bool trans_LSA(DisasContext *ctx, arg_rtype *a)
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{
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return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa);
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}
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static bool trans_DLSA(DisasContext *ctx, arg_rtype *a)
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{
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return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa);
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}
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bool decode_isa_rel6(DisasContext *ctx, uint32_t insn)
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{
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if (TARGET_LONG_BITS == 64 && decode_mips64r6(ctx, insn)) {
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return true;
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}
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return decode_mips32r6(ctx, insn);
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}
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