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qemu-patch-raspberry4/hw/riscv
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KONRAD Frederic 17b9751e85
riscv: spike: allow base == 0 
The sanity check on base doesn't allow htif to be mapped @0. Check if the
symbol exists instead so we can map it where we want.

Reviewed-by: Michael Clark <mjc@sifive.com>
Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com>
Signed-off-by: Michael Clark <mjc@sifive.com>

Message-Id: <1525360636-18229-2-git-send-email-frederic.konrad@adacore.com>
2018-05-09 07:57:32 +12:00
..
Makefile.objs RISC-V Build Infrastructure 2018-03-07 08:30:28 +13:00
riscv_hart.c RISC-V HART Array 2018-03-07 08:30:28 +13:00
riscv_htif.c riscv: spike: allow base == 0 2018-05-09 07:57:32 +12:00
sifive_clint.c SiFive RISC-V CLINT Block 2018-03-07 08:30:28 +13:00
sifive_e.c Change references to serial_hds[] to serial_hd() 2018-04-26 13:57:00 +01:00
sifive_plic.c SiFive RISC-V PLIC Block 2018-03-07 08:30:28 +13:00
sifive_prci.c SiFive RISC-V PRCI Block 2018-03-07 08:30:28 +13:00
sifive_test.c SiFive RISC-V Test Finisher 2018-03-07 08:30:28 +13:00
sifive_u.c Change references to serial_hds[] to serial_hd() 2018-04-26 13:57:00 +01:00
sifive_uart.c SiFive RISC-V UART Device 2018-03-07 08:30:28 +13:00
spike.c Change references to serial_hds[] to serial_hd() 2018-04-26 13:57:00 +01:00
virt.c Change references to serial_hds[] to serial_hd() 2018-04-26 13:57:00 +01:00