Currently the ptimer design uses a QEMU bottom-half as its mechanism for calling back into the device model using the ptimer when the timer has expired. Unfortunately this design is fatally flawed, because it means that there is a lag between the ptimer updating its own state and the device callback function updating device state, and guest accesses to device registers between the two can return inconsistent device state. We want to replace the bottom-half design with one where the guest device's callback is called either immediately (when the ptimer triggers by timeout) or when the device model code closes a transaction-begin/end section (when the ptimer triggers because the device model changed the ptimer's count value or other state). As the first step, rename ptimer_init() to ptimer_init_with_bh(), to free up the ptimer_init() name for the new API. We can then convert all the ptimer users away from ptimer_init_with_bh() before removing it entirely. (Commit created with git grep -l ptimer_init | xargs sed -i -e 's/ptimer_init/ptimer_init_with_bh/' and three overlong lines folded by hand.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20191008171740.9679-2-peter.maydell@linaro.org
294 lines
7.8 KiB
C
294 lines
7.8 KiB
C
/*
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* Block model of System timer present in
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* Microsemi's SmartFusion2 and SmartFusion SoCs.
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*
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* Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "qemu/main-loop.h"
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#include "qemu/module.h"
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#include "qemu/log.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#include "hw/timer/mss-timer.h"
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#include "migration/vmstate.h"
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#ifndef MSS_TIMER_ERR_DEBUG
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#define MSS_TIMER_ERR_DEBUG 0
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#endif
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#define DB_PRINT_L(lvl, fmt, args...) do { \
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if (MSS_TIMER_ERR_DEBUG >= lvl) { \
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qemu_log("%s: " fmt "\n", __func__, ## args); \
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} \
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} while (0)
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#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
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#define R_TIM_VAL 0
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#define R_TIM_LOADVAL 1
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#define R_TIM_BGLOADVAL 2
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#define R_TIM_CTRL 3
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#define R_TIM_RIS 4
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#define R_TIM_MIS 5
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#define TIMER_CTRL_ENBL (1 << 0)
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#define TIMER_CTRL_ONESHOT (1 << 1)
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#define TIMER_CTRL_INTR (1 << 2)
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#define TIMER_RIS_ACK (1 << 0)
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#define TIMER_RST_CLR (1 << 6)
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#define TIMER_MODE (1 << 0)
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static void timer_update_irq(struct Msf2Timer *st)
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{
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bool isr, ier;
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isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK);
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ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR);
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qemu_set_irq(st->irq, (ier && isr));
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}
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static void timer_update(struct Msf2Timer *st)
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{
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uint64_t count;
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if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL)) {
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ptimer_stop(st->ptimer);
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return;
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}
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count = st->regs[R_TIM_LOADVAL];
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ptimer_set_limit(st->ptimer, count, 1);
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ptimer_run(st->ptimer, 1);
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}
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static uint64_t
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timer_read(void *opaque, hwaddr offset, unsigned int size)
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{
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MSSTimerState *t = opaque;
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hwaddr addr;
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struct Msf2Timer *st;
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uint32_t ret = 0;
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int timer = 0;
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int isr;
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int ier;
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addr = offset >> 2;
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/*
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* Two independent timers has same base address.
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* Based on address passed figure out which timer is being used.
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*/
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if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) {
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timer = 1;
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addr -= R_TIM1_MAX;
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}
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st = &t->timers[timer];
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switch (addr) {
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case R_TIM_VAL:
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ret = ptimer_get_count(st->ptimer);
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break;
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case R_TIM_MIS:
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isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK);
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ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR);
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ret = ier & isr;
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break;
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default:
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if (addr < R_TIM1_MAX) {
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ret = st->regs[addr];
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} else {
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qemu_log_mask(LOG_GUEST_ERROR,
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TYPE_MSS_TIMER": 64-bit mode not supported\n");
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return ret;
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}
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break;
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}
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DB_PRINT("timer=%d 0x%" HWADDR_PRIx "=0x%" PRIx32, timer, offset,
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ret);
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return ret;
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}
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static void
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timer_write(void *opaque, hwaddr offset,
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uint64_t val64, unsigned int size)
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{
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MSSTimerState *t = opaque;
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hwaddr addr;
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struct Msf2Timer *st;
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int timer = 0;
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uint32_t value = val64;
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addr = offset >> 2;
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/*
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* Two independent timers has same base address.
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* Based on addr passed figure out which timer is being used.
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*/
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if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) {
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timer = 1;
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addr -= R_TIM1_MAX;
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}
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st = &t->timers[timer];
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DB_PRINT("addr=0x%" HWADDR_PRIx " val=0x%" PRIx32 " (timer=%d)", offset,
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value, timer);
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switch (addr) {
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case R_TIM_CTRL:
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st->regs[R_TIM_CTRL] = value;
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timer_update(st);
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break;
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case R_TIM_RIS:
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if (value & TIMER_RIS_ACK) {
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st->regs[R_TIM_RIS] &= ~TIMER_RIS_ACK;
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}
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break;
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case R_TIM_LOADVAL:
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st->regs[R_TIM_LOADVAL] = value;
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if (st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL) {
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timer_update(st);
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}
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break;
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case R_TIM_BGLOADVAL:
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st->regs[R_TIM_BGLOADVAL] = value;
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st->regs[R_TIM_LOADVAL] = value;
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break;
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case R_TIM_VAL:
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case R_TIM_MIS:
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break;
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default:
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if (addr < R_TIM1_MAX) {
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st->regs[addr] = value;
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} else {
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qemu_log_mask(LOG_GUEST_ERROR,
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TYPE_MSS_TIMER": 64-bit mode not supported\n");
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return;
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}
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break;
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}
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timer_update_irq(st);
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}
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static const MemoryRegionOps timer_ops = {
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.read = timer_read,
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.write = timer_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 1,
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.max_access_size = 4
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}
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};
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static void timer_hit(void *opaque)
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{
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struct Msf2Timer *st = opaque;
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st->regs[R_TIM_RIS] |= TIMER_RIS_ACK;
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if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ONESHOT)) {
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timer_update(st);
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}
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timer_update_irq(st);
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}
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static void mss_timer_init(Object *obj)
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{
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MSSTimerState *t = MSS_TIMER(obj);
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int i;
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/* Init all the ptimers. */
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for (i = 0; i < NUM_TIMERS; i++) {
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struct Msf2Timer *st = &t->timers[i];
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st->bh = qemu_bh_new(timer_hit, st);
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st->ptimer = ptimer_init_with_bh(st->bh, PTIMER_POLICY_DEFAULT);
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ptimer_set_freq(st->ptimer, t->freq_hz);
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sysbus_init_irq(SYS_BUS_DEVICE(obj), &st->irq);
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}
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memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, TYPE_MSS_TIMER,
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NUM_TIMERS * R_TIM1_MAX * 4);
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sysbus_init_mmio(SYS_BUS_DEVICE(obj), &t->mmio);
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}
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static const VMStateDescription vmstate_timers = {
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.name = "mss-timer-block",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_PTIMER(ptimer, struct Msf2Timer),
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VMSTATE_UINT32_ARRAY(regs, struct Msf2Timer, R_TIM1_MAX),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_mss_timer = {
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.name = TYPE_MSS_TIMER,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(freq_hz, MSSTimerState),
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VMSTATE_STRUCT_ARRAY(timers, MSSTimerState, NUM_TIMERS, 0,
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vmstate_timers, struct Msf2Timer),
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VMSTATE_END_OF_LIST()
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}
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};
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static Property mss_timer_properties[] = {
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/* Libero GUI shows 100Mhz as default for clocks */
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DEFINE_PROP_UINT32("clock-frequency", MSSTimerState, freq_hz,
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100 * 1000000),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void mss_timer_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->props = mss_timer_properties;
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dc->vmsd = &vmstate_mss_timer;
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}
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static const TypeInfo mss_timer_info = {
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.name = TYPE_MSS_TIMER,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(MSSTimerState),
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.instance_init = mss_timer_init,
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.class_init = mss_timer_class_init,
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};
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static void mss_timer_register_types(void)
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{
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type_register_static(&mss_timer_info);
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}
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type_init(mss_timer_register_types)
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