c7b9517188
Previous CSR code uses csr_read_helper and csr_write_helper to update CSR registers however this interface prevents atomic read/modify/write CSR operations; in addition there is no trap-free method to access to CSRs due to the monolithic CSR functions call longjmp. The current iCSR interface is not safe to be called by target/riscv/gdbstub.c as privilege checks or missing CSRs may call longjmp to generate exceptions. It needs to indicate existence so traps can be generated in the CSR instruction helpers. This commit moves CSR access from the monolithic switch statements in target/riscv/op_helper.c into modular read/write functions in target/riscv/csr.c using a new function pointer table for dispatch (which can later be used to allow CPUs to hook up model specific CSRs). A read/modify/write interface is added to support atomic CSR operations and a non-trapping interface is added to allow exception-free access to CSRs by the debugger. The CSR functions and CSR dispatch table are ordered to match The RISC-V Instruction Set Manual, Volume II: Privileged Architecture Version 1.10, 2.2 CSR Listing. An API is added to allow derived cpu instances to modify or implement new CSR operations. Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
69 lines
2.1 KiB
C
69 lines
2.1 KiB
C
/*
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* RISC-V GDB Server Stub
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "exec/gdbstub.h"
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#include "cpu.h"
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int riscv_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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if (n < 32) {
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return gdb_get_regl(mem_buf, env->gpr[n]);
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} else if (n == 32) {
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return gdb_get_regl(mem_buf, env->pc);
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} else if (n < 65) {
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return gdb_get_reg64(mem_buf, env->fpr[n - 33]);
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} else if (n < 4096 + 65) {
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target_ulong val = 0;
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if (riscv_csrrw(env, n - 65, &val, 0, 0) == 0) {
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return gdb_get_regl(mem_buf, val);
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}
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}
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return 0;
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}
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int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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if (n == 0) {
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/* discard writes to x0 */
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return sizeof(target_ulong);
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} else if (n < 32) {
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env->gpr[n] = ldtul_p(mem_buf);
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return sizeof(target_ulong);
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} else if (n == 32) {
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env->pc = ldtul_p(mem_buf);
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return sizeof(target_ulong);
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} else if (n < 65) {
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env->fpr[n - 33] = ldq_p(mem_buf); /* always 64-bit */
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return sizeof(uint64_t);
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} else if (n < 4096 + 65) {
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target_ulong val = ldtul_p(mem_buf);
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if (riscv_csrrw(env, n - 65, NULL, val, -1) == 0) {
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return sizeof(target_ulong);
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}
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}
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return 0;
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}
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