Code change produced with: $ git grep '#include "exec/ioport.h"' hw | \ cut -d: -f-1 | \ xargs egrep -Li "(portio|cpu_(in|out).\()" | \ xargs sed -i.bak '/#include "exec\/ioport.h"/d' Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180528232719.4721-11-f4bug@amsat.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Marcel Apfelbaum<marcel.apfelbaum@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
360 lines
10 KiB
C
360 lines
10 KiB
C
/*
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* QEMU<->ACPI BIOS PCI hotplug interface
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*
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* QEMU supports PCI hotplug via ACPI. This module
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* implements the interface between QEMU and the ACPI BIOS.
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* Interface specification - see docs/specs/acpi_pci_hotplug.txt
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*
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* Copyright (c) 2013, Red Hat Inc, Michael S. Tsirkin (mst@redhat.com)
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* Copyright (c) 2006 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License version 2 as published by the Free Software Foundation.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>
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*
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* Contributions after 2012-01-13 are licensed under the terms of the
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* GNU GPL, version 2 or (at your option) any later version.
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*/
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#include "qemu/osdep.h"
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#include "hw/acpi/pcihp.h"
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#include "hw/hw.h"
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#include "hw/i386/pc.h"
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#include "hw/pci/pci.h"
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#include "hw/acpi/acpi.h"
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#include "sysemu/sysemu.h"
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#include "exec/address-spaces.h"
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#include "hw/pci/pci_bus.h"
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#include "qapi/error.h"
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#include "qom/qom-qobject.h"
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//#define DEBUG
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#ifdef DEBUG
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# define ACPI_PCIHP_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
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#else
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# define ACPI_PCIHP_DPRINTF(format, ...) do { } while (0)
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#endif
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#define ACPI_PCIHP_ADDR 0xae00
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#define ACPI_PCIHP_SIZE 0x0014
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#define PCI_UP_BASE 0x0000
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#define PCI_DOWN_BASE 0x0004
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#define PCI_EJ_BASE 0x0008
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#define PCI_RMV_BASE 0x000c
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#define PCI_SEL_BASE 0x0010
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typedef struct AcpiPciHpFind {
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int bsel;
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PCIBus *bus;
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} AcpiPciHpFind;
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static int acpi_pcihp_get_bsel(PCIBus *bus)
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{
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Error *local_err = NULL;
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uint64_t bsel = object_property_get_uint(OBJECT(bus), ACPI_PCIHP_PROP_BSEL,
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&local_err);
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if (local_err || bsel >= ACPI_PCIHP_MAX_HOTPLUG_BUS) {
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if (local_err) {
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error_free(local_err);
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}
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return -1;
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} else {
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return bsel;
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}
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}
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/* Assign BSEL property to all buses. In the future, this can be changed
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* to only assign to buses that support hotplug.
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*/
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static void *acpi_set_bsel(PCIBus *bus, void *opaque)
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{
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unsigned *bsel_alloc = opaque;
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unsigned *bus_bsel;
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if (qbus_is_hotpluggable(BUS(bus))) {
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bus_bsel = g_malloc(sizeof *bus_bsel);
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*bus_bsel = (*bsel_alloc)++;
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object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL,
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bus_bsel, &error_abort);
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}
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return bsel_alloc;
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}
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static void acpi_set_pci_info(void)
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{
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static bool bsel_is_set;
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PCIBus *bus;
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unsigned bsel_alloc = ACPI_PCIHP_BSEL_DEFAULT;
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if (bsel_is_set) {
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return;
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}
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bsel_is_set = true;
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bus = find_i440fx(); /* TODO: Q35 support */
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if (bus) {
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/* Scan all PCI buses. Set property to enable acpi based hotplug. */
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pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc);
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}
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}
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static void acpi_pcihp_test_hotplug_bus(PCIBus *bus, void *opaque)
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{
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AcpiPciHpFind *find = opaque;
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if (find->bsel == acpi_pcihp_get_bsel(bus)) {
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find->bus = bus;
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}
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}
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static PCIBus *acpi_pcihp_find_hotplug_bus(AcpiPciHpState *s, int bsel)
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{
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AcpiPciHpFind find = { .bsel = bsel, .bus = NULL };
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if (bsel < 0) {
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return NULL;
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}
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pci_for_each_bus(s->root, acpi_pcihp_test_hotplug_bus, &find);
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/* Make bsel 0 eject root bus if bsel property is not set,
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* for compatibility with non acpi setups.
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* TODO: really needed?
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*/
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if (!bsel && !find.bus) {
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find.bus = s->root;
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}
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return find.bus;
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}
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static bool acpi_pcihp_pc_no_hotplug(AcpiPciHpState *s, PCIDevice *dev)
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{
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PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
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DeviceClass *dc = DEVICE_GET_CLASS(dev);
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/*
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* ACPI doesn't allow hotplug of bridge devices. Don't allow
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* hot-unplug of bridge devices unless they were added by hotplug
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* (and so, not described by acpi).
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*/
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return (pc->is_bridge && !dev->qdev.hotplugged) || !dc->hotpluggable;
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}
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static void acpi_pcihp_eject_slot(AcpiPciHpState *s, unsigned bsel, unsigned slots)
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{
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BusChild *kid, *next;
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int slot = ctz32(slots);
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PCIBus *bus = acpi_pcihp_find_hotplug_bus(s, bsel);
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if (!bus) {
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return;
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}
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/* Mark request as complete */
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s->acpi_pcihp_pci_status[bsel].down &= ~(1U << slot);
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s->acpi_pcihp_pci_status[bsel].up &= ~(1U << slot);
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QTAILQ_FOREACH_SAFE(kid, &bus->qbus.children, sibling, next) {
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DeviceState *qdev = kid->child;
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PCIDevice *dev = PCI_DEVICE(qdev);
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if (PCI_SLOT(dev->devfn) == slot) {
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if (!acpi_pcihp_pc_no_hotplug(s, dev)) {
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object_unparent(OBJECT(qdev));
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}
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}
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}
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}
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static void acpi_pcihp_update_hotplug_bus(AcpiPciHpState *s, int bsel)
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{
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BusChild *kid, *next;
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PCIBus *bus = acpi_pcihp_find_hotplug_bus(s, bsel);
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/* Execute any pending removes during reset */
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while (s->acpi_pcihp_pci_status[bsel].down) {
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acpi_pcihp_eject_slot(s, bsel, s->acpi_pcihp_pci_status[bsel].down);
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}
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s->acpi_pcihp_pci_status[bsel].hotplug_enable = ~0;
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if (!bus) {
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return;
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}
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QTAILQ_FOREACH_SAFE(kid, &bus->qbus.children, sibling, next) {
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DeviceState *qdev = kid->child;
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PCIDevice *pdev = PCI_DEVICE(qdev);
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int slot = PCI_SLOT(pdev->devfn);
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if (acpi_pcihp_pc_no_hotplug(s, pdev)) {
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s->acpi_pcihp_pci_status[bsel].hotplug_enable &= ~(1U << slot);
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}
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}
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}
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static void acpi_pcihp_update(AcpiPciHpState *s)
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{
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int i;
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for (i = 0; i < ACPI_PCIHP_MAX_HOTPLUG_BUS; ++i) {
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acpi_pcihp_update_hotplug_bus(s, i);
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}
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}
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void acpi_pcihp_reset(AcpiPciHpState *s)
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{
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acpi_set_pci_info();
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acpi_pcihp_update(s);
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}
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void acpi_pcihp_device_plug_cb(HotplugHandler *hotplug_dev, AcpiPciHpState *s,
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DeviceState *dev, Error **errp)
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{
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PCIDevice *pdev = PCI_DEVICE(dev);
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int slot = PCI_SLOT(pdev->devfn);
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int bsel = acpi_pcihp_get_bsel(pci_get_bus(pdev));
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if (bsel < 0) {
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error_setg(errp, "Unsupported bus. Bus doesn't have property '"
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ACPI_PCIHP_PROP_BSEL "' set");
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return;
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}
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/* Don't send event when device is enabled during qemu machine creation:
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* it is present on boot, no hotplug event is necessary. We do send an
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* event when the device is disabled later. */
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if (!dev->hotplugged) {
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return;
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}
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s->acpi_pcihp_pci_status[bsel].up |= (1U << slot);
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acpi_send_event(DEVICE(hotplug_dev), ACPI_PCI_HOTPLUG_STATUS);
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}
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void acpi_pcihp_device_unplug_cb(HotplugHandler *hotplug_dev, AcpiPciHpState *s,
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DeviceState *dev, Error **errp)
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{
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PCIDevice *pdev = PCI_DEVICE(dev);
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int slot = PCI_SLOT(pdev->devfn);
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int bsel = acpi_pcihp_get_bsel(pci_get_bus(pdev));
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if (bsel < 0) {
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error_setg(errp, "Unsupported bus. Bus doesn't have property '"
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ACPI_PCIHP_PROP_BSEL "' set");
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return;
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}
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s->acpi_pcihp_pci_status[bsel].down |= (1U << slot);
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acpi_send_event(DEVICE(hotplug_dev), ACPI_PCI_HOTPLUG_STATUS);
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}
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static uint64_t pci_read(void *opaque, hwaddr addr, unsigned int size)
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{
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AcpiPciHpState *s = opaque;
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uint32_t val = 0;
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int bsel = s->hotplug_select;
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if (bsel < 0 || bsel >= ACPI_PCIHP_MAX_HOTPLUG_BUS) {
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return 0;
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}
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switch (addr) {
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case PCI_UP_BASE:
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val = s->acpi_pcihp_pci_status[bsel].up;
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if (!s->legacy_piix) {
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s->acpi_pcihp_pci_status[bsel].up = 0;
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}
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ACPI_PCIHP_DPRINTF("pci_up_read %" PRIu32 "\n", val);
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break;
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case PCI_DOWN_BASE:
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val = s->acpi_pcihp_pci_status[bsel].down;
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ACPI_PCIHP_DPRINTF("pci_down_read %" PRIu32 "\n", val);
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break;
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case PCI_EJ_BASE:
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/* No feature defined yet */
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ACPI_PCIHP_DPRINTF("pci_features_read %" PRIu32 "\n", val);
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break;
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case PCI_RMV_BASE:
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val = s->acpi_pcihp_pci_status[bsel].hotplug_enable;
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ACPI_PCIHP_DPRINTF("pci_rmv_read %" PRIu32 "\n", val);
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break;
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case PCI_SEL_BASE:
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val = s->hotplug_select;
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ACPI_PCIHP_DPRINTF("pci_sel_read %" PRIu32 "\n", val);
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default:
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break;
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}
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return val;
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}
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static void pci_write(void *opaque, hwaddr addr, uint64_t data,
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unsigned int size)
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{
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AcpiPciHpState *s = opaque;
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switch (addr) {
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case PCI_EJ_BASE:
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if (s->hotplug_select >= ACPI_PCIHP_MAX_HOTPLUG_BUS) {
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break;
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}
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acpi_pcihp_eject_slot(s, s->hotplug_select, data);
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ACPI_PCIHP_DPRINTF("pciej write %" HWADDR_PRIx " <== %" PRIu64 "\n",
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addr, data);
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break;
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case PCI_SEL_BASE:
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s->hotplug_select = s->legacy_piix ? ACPI_PCIHP_BSEL_DEFAULT : data;
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ACPI_PCIHP_DPRINTF("pcisel write %" HWADDR_PRIx " <== %" PRIu64 "\n",
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addr, data);
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default:
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break;
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}
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}
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static const MemoryRegionOps acpi_pcihp_io_ops = {
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.read = pci_read,
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.write = pci_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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void acpi_pcihp_init(Object *owner, AcpiPciHpState *s, PCIBus *root_bus,
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MemoryRegion *address_space_io, bool bridges_enabled)
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{
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s->io_len = ACPI_PCIHP_SIZE;
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s->io_base = ACPI_PCIHP_ADDR;
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s->root= root_bus;
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s->legacy_piix = !bridges_enabled;
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memory_region_init_io(&s->io, owner, &acpi_pcihp_io_ops, s,
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"acpi-pci-hotplug", s->io_len);
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memory_region_add_subregion(address_space_io, s->io_base, &s->io);
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object_property_add_uint16_ptr(owner, ACPI_PCIHP_IO_BASE_PROP, &s->io_base,
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&error_abort);
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object_property_add_uint16_ptr(owner, ACPI_PCIHP_IO_LEN_PROP, &s->io_len,
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&error_abort);
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}
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const VMStateDescription vmstate_acpi_pcihp_pci_status = {
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.name = "acpi_pcihp_pci_status",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(up, AcpiPciHpPciStatus),
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VMSTATE_UINT32(down, AcpiPciHpPciStatus),
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VMSTATE_END_OF_LIST()
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}
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};
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