The APB frequency can be calculated directly when needed from the HPLL_PARAM and CLK_SEL register values. This removes useless state in the model. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20190904070506.1052-11-clg@kaod.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
581 lines
16 KiB
C
581 lines
16 KiB
C
/*
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* ASPEED AST2400 Timer
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*
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* Andrew Jeffery <andrew@aj.id.au>
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*
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* Copyright (C) 2016 IBM Corp.
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "hw/irq.h"
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#include "hw/sysbus.h"
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#include "hw/timer/aspeed_timer.h"
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#include "migration/vmstate.h"
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#include "qemu/bitops.h"
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#include "qemu/timer.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "trace.h"
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#define TIMER_NR_REGS 4
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#define TIMER_CTRL_BITS 4
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#define TIMER_CTRL_MASK ((1 << TIMER_CTRL_BITS) - 1)
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#define TIMER_CLOCK_USE_EXT true
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#define TIMER_CLOCK_EXT_HZ 1000000
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#define TIMER_CLOCK_USE_APB false
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#define TIMER_REG_STATUS 0
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#define TIMER_REG_RELOAD 1
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#define TIMER_REG_MATCH_FIRST 2
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#define TIMER_REG_MATCH_SECOND 3
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#define TIMER_FIRST_CAP_PULSE 4
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enum timer_ctrl_op {
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op_enable = 0,
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op_external_clock,
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op_overflow_interrupt,
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op_pulse_enable
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};
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/*
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* Minimum value of the reload register to filter out short period
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* timers which have a noticeable impact in emulation. 5us should be
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* enough, use 20us for "safety".
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*/
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#define TIMER_MIN_NS (20 * SCALE_US)
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/**
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* Avoid mutual references between AspeedTimerCtrlState and AspeedTimer
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* structs, as it's a waste of memory. The ptimer BH callback needs to know
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* whether a specific AspeedTimer is enabled, but this information is held in
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* AspeedTimerCtrlState. So, provide a helper to hoist ourselves from an
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* arbitrary AspeedTimer to AspeedTimerCtrlState.
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*/
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static inline AspeedTimerCtrlState *timer_to_ctrl(AspeedTimer *t)
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{
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const AspeedTimer (*timers)[] = (void *)t - (t->id * sizeof(*t));
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return container_of(timers, AspeedTimerCtrlState, timers);
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}
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static inline bool timer_ctrl_status(AspeedTimer *t, enum timer_ctrl_op op)
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{
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return !!(timer_to_ctrl(t)->ctrl & BIT(t->id * TIMER_CTRL_BITS + op));
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}
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static inline bool timer_enabled(AspeedTimer *t)
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{
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return timer_ctrl_status(t, op_enable);
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}
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static inline bool timer_overflow_interrupt(AspeedTimer *t)
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{
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return timer_ctrl_status(t, op_overflow_interrupt);
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}
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static inline bool timer_can_pulse(AspeedTimer *t)
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{
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return t->id >= TIMER_FIRST_CAP_PULSE;
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}
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static inline bool timer_external_clock(AspeedTimer *t)
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{
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return timer_ctrl_status(t, op_external_clock);
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}
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static inline uint32_t calculate_rate(struct AspeedTimer *t)
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{
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AspeedTimerCtrlState *s = timer_to_ctrl(t);
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return timer_external_clock(t) ? TIMER_CLOCK_EXT_HZ :
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aspeed_scu_get_apb_freq(s->scu);
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}
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static inline uint32_t calculate_ticks(struct AspeedTimer *t, uint64_t now_ns)
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{
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uint64_t delta_ns = now_ns - MIN(now_ns, t->start);
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uint32_t rate = calculate_rate(t);
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uint64_t ticks = muldiv64(delta_ns, rate, NANOSECONDS_PER_SECOND);
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return t->reload - MIN(t->reload, ticks);
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}
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static uint32_t calculate_min_ticks(AspeedTimer *t, uint32_t value)
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{
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uint32_t rate = calculate_rate(t);
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uint32_t min_ticks = muldiv64(TIMER_MIN_NS, rate, NANOSECONDS_PER_SECOND);
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return value < min_ticks ? min_ticks : value;
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}
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static inline uint64_t calculate_time(struct AspeedTimer *t, uint32_t ticks)
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{
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uint64_t delta_ns;
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uint64_t delta_ticks;
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delta_ticks = t->reload - MIN(t->reload, ticks);
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delta_ns = muldiv64(delta_ticks, NANOSECONDS_PER_SECOND, calculate_rate(t));
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return t->start + delta_ns;
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}
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static inline uint32_t calculate_match(struct AspeedTimer *t, int i)
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{
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return t->match[i] < t->reload ? t->match[i] : 0;
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}
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static uint64_t calculate_next(struct AspeedTimer *t)
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{
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uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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uint64_t next;
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/*
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* We don't know the relationship between the values in the match
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* registers, so sort using MAX/MIN/zero. We sort in that order as
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* the timer counts down to zero.
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*/
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next = calculate_time(t, MAX(calculate_match(t, 0), calculate_match(t, 1)));
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if (now < next) {
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return next;
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}
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next = calculate_time(t, MIN(calculate_match(t, 0), calculate_match(t, 1)));
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if (now < next) {
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return next;
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}
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next = calculate_time(t, 0);
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if (now < next) {
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return next;
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}
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/* We've missed all deadlines, fire interrupt and try again */
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timer_del(&t->timer);
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if (timer_overflow_interrupt(t)) {
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t->level = !t->level;
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qemu_set_irq(t->irq, t->level);
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}
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next = MAX(MAX(calculate_match(t, 0), calculate_match(t, 1)), 0);
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t->start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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return calculate_time(t, next);
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}
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static void aspeed_timer_mod(AspeedTimer *t)
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{
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uint64_t next = calculate_next(t);
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if (next) {
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timer_mod(&t->timer, next);
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}
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}
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static void aspeed_timer_expire(void *opaque)
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{
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AspeedTimer *t = opaque;
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bool interrupt = false;
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uint32_t ticks;
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if (!timer_enabled(t)) {
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return;
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}
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ticks = calculate_ticks(t, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
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if (!ticks) {
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interrupt = timer_overflow_interrupt(t) || !t->match[0] || !t->match[1];
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} else if (ticks <= MIN(t->match[0], t->match[1])) {
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interrupt = true;
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} else if (ticks <= MAX(t->match[0], t->match[1])) {
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interrupt = true;
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}
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if (interrupt) {
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t->level = !t->level;
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qemu_set_irq(t->irq, t->level);
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}
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aspeed_timer_mod(t);
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}
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static uint64_t aspeed_timer_get_value(AspeedTimer *t, int reg)
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{
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uint64_t value;
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switch (reg) {
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case TIMER_REG_STATUS:
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if (timer_enabled(t)) {
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value = calculate_ticks(t, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
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} else {
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value = t->reload;
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}
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break;
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case TIMER_REG_RELOAD:
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value = t->reload;
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break;
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case TIMER_REG_MATCH_FIRST:
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case TIMER_REG_MATCH_SECOND:
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value = t->match[reg - 2];
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "%s: Programming error: unexpected reg: %d\n",
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__func__, reg);
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value = 0;
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break;
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}
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return value;
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}
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static uint64_t aspeed_timer_read(void *opaque, hwaddr offset, unsigned size)
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{
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AspeedTimerCtrlState *s = opaque;
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const int reg = (offset & 0xf) / 4;
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uint64_t value;
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switch (offset) {
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case 0x30: /* Control Register */
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value = s->ctrl;
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break;
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case 0x34: /* Control Register 2 */
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value = s->ctrl2;
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break;
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case 0x00 ... 0x2c: /* Timers 1 - 4 */
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value = aspeed_timer_get_value(&s->timers[(offset >> 4)], reg);
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break;
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case 0x40 ... 0x8c: /* Timers 5 - 8 */
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value = aspeed_timer_get_value(&s->timers[(offset >> 4) - 1], reg);
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break;
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/* Illegal */
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case 0x38:
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case 0x3C:
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
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__func__, offset);
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value = 0;
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break;
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}
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trace_aspeed_timer_read(offset, size, value);
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return value;
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}
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static void aspeed_timer_set_value(AspeedTimerCtrlState *s, int timer, int reg,
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uint32_t value)
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{
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AspeedTimer *t;
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uint32_t old_reload;
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trace_aspeed_timer_set_value(timer, reg, value);
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t = &s->timers[timer];
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switch (reg) {
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case TIMER_REG_RELOAD:
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old_reload = t->reload;
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t->reload = calculate_min_ticks(t, value);
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/* If the reload value was not previously set, or zero, and
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* the current value is valid, try to start the timer if it is
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* enabled.
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*/
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if (old_reload || !t->reload) {
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break;
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}
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case TIMER_REG_STATUS:
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if (timer_enabled(t)) {
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uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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int64_t delta = (int64_t) value - (int64_t) calculate_ticks(t, now);
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uint32_t rate = calculate_rate(t);
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if (delta >= 0) {
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t->start += muldiv64(delta, NANOSECONDS_PER_SECOND, rate);
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} else {
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t->start -= muldiv64(-delta, NANOSECONDS_PER_SECOND, rate);
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}
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aspeed_timer_mod(t);
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}
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break;
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case TIMER_REG_MATCH_FIRST:
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case TIMER_REG_MATCH_SECOND:
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t->match[reg - 2] = value;
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if (timer_enabled(t)) {
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aspeed_timer_mod(t);
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}
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "%s: Programming error: unexpected reg: %d\n",
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__func__, reg);
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break;
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}
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}
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/* Control register operations are broken out into helpers that can be
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* explicitly called on aspeed_timer_reset(), but also from
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* aspeed_timer_ctrl_op().
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*/
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static void aspeed_timer_ctrl_enable(AspeedTimer *t, bool enable)
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{
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trace_aspeed_timer_ctrl_enable(t->id, enable);
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if (enable) {
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t->start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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aspeed_timer_mod(t);
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} else {
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timer_del(&t->timer);
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}
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}
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static void aspeed_timer_ctrl_external_clock(AspeedTimer *t, bool enable)
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{
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trace_aspeed_timer_ctrl_external_clock(t->id, enable);
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}
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static void aspeed_timer_ctrl_overflow_interrupt(AspeedTimer *t, bool enable)
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{
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trace_aspeed_timer_ctrl_overflow_interrupt(t->id, enable);
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}
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static void aspeed_timer_ctrl_pulse_enable(AspeedTimer *t, bool enable)
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{
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if (timer_can_pulse(t)) {
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trace_aspeed_timer_ctrl_pulse_enable(t->id, enable);
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} else {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Timer does not support pulse mode\n", __func__);
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}
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}
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/**
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* Given the actions are fixed in number and completely described in helper
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* functions, dispatch with a lookup table rather than manage control flow with
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* a switch statement.
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*/
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static void (*const ctrl_ops[])(AspeedTimer *, bool) = {
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[op_enable] = aspeed_timer_ctrl_enable,
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[op_external_clock] = aspeed_timer_ctrl_external_clock,
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[op_overflow_interrupt] = aspeed_timer_ctrl_overflow_interrupt,
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[op_pulse_enable] = aspeed_timer_ctrl_pulse_enable,
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};
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/**
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* Conditionally affect changes chosen by a timer's control bit.
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*
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* The aspeed_timer_ctrl_op() interface is convenient for the
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* aspeed_timer_set_ctrl() function as the "no change" early exit can be
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* calculated for all operations, which cleans up the caller code. However the
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* interface isn't convenient for the reset function where we want to enter a
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* specific state without artificially constructing old and new values that
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* will fall through the change guard (and motivates extracting the actions
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* out to helper functions).
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*
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* @t: The timer to manipulate
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* @op: The type of operation to be performed
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* @old: The old state of the timer's control bits
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* @new: The incoming state for the timer's control bits
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*/
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static void aspeed_timer_ctrl_op(AspeedTimer *t, enum timer_ctrl_op op,
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uint8_t old, uint8_t new)
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{
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const uint8_t mask = BIT(op);
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const bool enable = !!(new & mask);
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const bool changed = ((old ^ new) & mask);
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if (!changed) {
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return;
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}
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ctrl_ops[op](t, enable);
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}
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static void aspeed_timer_set_ctrl(AspeedTimerCtrlState *s, uint32_t reg)
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{
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int i;
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int shift;
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uint8_t t_old, t_new;
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AspeedTimer *t;
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const uint8_t enable_mask = BIT(op_enable);
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/* Handle a dependency between the 'enable' and remaining three
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* configuration bits - i.e. if more than one bit in the control set has
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* changed, including the 'enable' bit, then we want either disable the
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* timer and perform configuration, or perform configuration and then
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* enable the timer
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*/
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for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
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t = &s->timers[i];
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shift = (i * TIMER_CTRL_BITS);
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t_old = (s->ctrl >> shift) & TIMER_CTRL_MASK;
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t_new = (reg >> shift) & TIMER_CTRL_MASK;
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/* If we are disabling, do so first */
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if ((t_old & enable_mask) && !(t_new & enable_mask)) {
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aspeed_timer_ctrl_enable(t, false);
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}
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aspeed_timer_ctrl_op(t, op_external_clock, t_old, t_new);
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aspeed_timer_ctrl_op(t, op_overflow_interrupt, t_old, t_new);
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aspeed_timer_ctrl_op(t, op_pulse_enable, t_old, t_new);
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/* If we are enabling, do so last */
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if (!(t_old & enable_mask) && (t_new & enable_mask)) {
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aspeed_timer_ctrl_enable(t, true);
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}
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}
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s->ctrl = reg;
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}
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static void aspeed_timer_set_ctrl2(AspeedTimerCtrlState *s, uint32_t value)
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{
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trace_aspeed_timer_set_ctrl2(value);
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}
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static void aspeed_timer_write(void *opaque, hwaddr offset, uint64_t value,
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unsigned size)
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{
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const uint32_t tv = (uint32_t)(value & 0xFFFFFFFF);
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const int reg = (offset & 0xf) / 4;
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AspeedTimerCtrlState *s = opaque;
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switch (offset) {
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/* Control Registers */
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case 0x30:
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aspeed_timer_set_ctrl(s, tv);
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break;
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case 0x34:
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aspeed_timer_set_ctrl2(s, tv);
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break;
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/* Timer Registers */
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case 0x00 ... 0x2c:
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aspeed_timer_set_value(s, (offset >> TIMER_NR_REGS), reg, tv);
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break;
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case 0x40 ... 0x8c:
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aspeed_timer_set_value(s, (offset >> TIMER_NR_REGS) - 1, reg, tv);
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break;
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/* Illegal */
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case 0x38:
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case 0x3C:
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
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__func__, offset);
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break;
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}
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}
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static const MemoryRegionOps aspeed_timer_ops = {
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.read = aspeed_timer_read,
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.write = aspeed_timer_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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.valid.unaligned = false,
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};
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static void aspeed_init_one_timer(AspeedTimerCtrlState *s, uint8_t id)
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{
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AspeedTimer *t = &s->timers[id];
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t->id = id;
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timer_init_ns(&t->timer, QEMU_CLOCK_VIRTUAL, aspeed_timer_expire, t);
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}
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static void aspeed_timer_realize(DeviceState *dev, Error **errp)
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{
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int i;
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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AspeedTimerCtrlState *s = ASPEED_TIMER(dev);
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Object *obj;
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Error *err = NULL;
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obj = object_property_get_link(OBJECT(dev), "scu", &err);
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if (!obj) {
|
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error_propagate_prepend(errp, err, "required link 'scu' not found: ");
|
|
return;
|
|
}
|
|
s->scu = ASPEED_SCU(obj);
|
|
|
|
for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
|
|
aspeed_init_one_timer(s, i);
|
|
sysbus_init_irq(sbd, &s->timers[i].irq);
|
|
}
|
|
memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_timer_ops, s,
|
|
TYPE_ASPEED_TIMER, 0x1000);
|
|
sysbus_init_mmio(sbd, &s->iomem);
|
|
}
|
|
|
|
static void aspeed_timer_reset(DeviceState *dev)
|
|
{
|
|
int i;
|
|
AspeedTimerCtrlState *s = ASPEED_TIMER(dev);
|
|
|
|
for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
|
|
AspeedTimer *t = &s->timers[i];
|
|
/* Explicitly call helpers to avoid any conditional behaviour through
|
|
* aspeed_timer_set_ctrl().
|
|
*/
|
|
aspeed_timer_ctrl_enable(t, false);
|
|
aspeed_timer_ctrl_external_clock(t, TIMER_CLOCK_USE_APB);
|
|
aspeed_timer_ctrl_overflow_interrupt(t, false);
|
|
aspeed_timer_ctrl_pulse_enable(t, false);
|
|
t->level = 0;
|
|
t->reload = 0;
|
|
t->match[0] = 0;
|
|
t->match[1] = 0;
|
|
}
|
|
s->ctrl = 0;
|
|
s->ctrl2 = 0;
|
|
}
|
|
|
|
static const VMStateDescription vmstate_aspeed_timer = {
|
|
.name = "aspeed.timer",
|
|
.version_id = 2,
|
|
.minimum_version_id = 2,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT8(id, AspeedTimer),
|
|
VMSTATE_INT32(level, AspeedTimer),
|
|
VMSTATE_TIMER(timer, AspeedTimer),
|
|
VMSTATE_UINT32(reload, AspeedTimer),
|
|
VMSTATE_UINT32_ARRAY(match, AspeedTimer, 2),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static const VMStateDescription vmstate_aspeed_timer_state = {
|
|
.name = "aspeed.timerctrl",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT32(ctrl, AspeedTimerCtrlState),
|
|
VMSTATE_UINT32(ctrl2, AspeedTimerCtrlState),
|
|
VMSTATE_STRUCT_ARRAY(timers, AspeedTimerCtrlState,
|
|
ASPEED_TIMER_NR_TIMERS, 1, vmstate_aspeed_timer,
|
|
AspeedTimer),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static void timer_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
dc->realize = aspeed_timer_realize;
|
|
dc->reset = aspeed_timer_reset;
|
|
dc->desc = "ASPEED Timer";
|
|
dc->vmsd = &vmstate_aspeed_timer_state;
|
|
}
|
|
|
|
static const TypeInfo aspeed_timer_info = {
|
|
.name = TYPE_ASPEED_TIMER,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(AspeedTimerCtrlState),
|
|
.class_init = timer_class_init,
|
|
};
|
|
|
|
static void aspeed_timer_register_types(void)
|
|
{
|
|
type_register_static(&aspeed_timer_info);
|
|
}
|
|
|
|
type_init(aspeed_timer_register_types)
|