In my "build everything" tree, changing sysemu/sysemu.h triggers a recompile of some 5400 out of 6600 objects (not counting tests and objects that don't depend on qemu/osdep.h). Almost a third of its inclusions are actually superfluous. Delete them. Downgrade two more to qapi/qapi-types-run-state.h, and move one from char/serial.h to char/serial.c. hw/semihosting/config.c, monitor/monitor.c, qdev-monitor.c, and stubs/semihost.c define variables declared in sysemu/sysemu.h without including it. The compiler is cool with that, but include it anyway. This doesn't reduce actual use much, as it's still included into widely included headers. The next commit will tackle that. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20190812052359.30071-27-armbru@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
201 lines
5 KiB
C
201 lines
5 KiB
C
/*
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* ARM SSE-200 Message Handling Unit (MHU)
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*
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* Copyright (c) 2019 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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/*
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* This is a model of the Message Handling Unit (MHU) which is part of the
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* Arm SSE-200 and documented in
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* http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "trace.h"
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#include "qapi/error.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "hw/registerfields.h"
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#include "hw/irq.h"
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#include "hw/misc/armsse-mhu.h"
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REG32(CPU0INTR_STAT, 0x0)
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REG32(CPU0INTR_SET, 0x4)
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REG32(CPU0INTR_CLR, 0x8)
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REG32(CPU1INTR_STAT, 0x10)
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REG32(CPU1INTR_SET, 0x14)
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REG32(CPU1INTR_CLR, 0x18)
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REG32(PID4, 0xfd0)
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REG32(PID5, 0xfd4)
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REG32(PID6, 0xfd8)
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REG32(PID7, 0xfdc)
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REG32(PID0, 0xfe0)
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REG32(PID1, 0xfe4)
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REG32(PID2, 0xfe8)
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REG32(PID3, 0xfec)
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REG32(CID0, 0xff0)
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REG32(CID1, 0xff4)
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REG32(CID2, 0xff8)
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REG32(CID3, 0xffc)
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/* Valid bits in the interrupt registers. If any are set the IRQ is raised */
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#define INTR_MASK 0xf
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/* PID/CID values */
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static const int armsse_mhu_id[] = {
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0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */
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0x56, 0xb8, 0x0b, 0x00, /* PID0..PID3 */
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0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
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};
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static void armsse_mhu_update(ARMSSEMHU *s)
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{
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qemu_set_irq(s->cpu0irq, s->cpu0intr != 0);
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qemu_set_irq(s->cpu1irq, s->cpu1intr != 0);
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}
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static uint64_t armsse_mhu_read(void *opaque, hwaddr offset, unsigned size)
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{
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ARMSSEMHU *s = ARMSSE_MHU(opaque);
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uint64_t r;
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switch (offset) {
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case A_CPU0INTR_STAT:
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r = s->cpu0intr;
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break;
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case A_CPU1INTR_STAT:
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r = s->cpu1intr;
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break;
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case A_PID4 ... A_CID3:
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r = armsse_mhu_id[(offset - A_PID4) / 4];
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break;
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case A_CPU0INTR_SET:
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case A_CPU0INTR_CLR:
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case A_CPU1INTR_SET:
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case A_CPU1INTR_CLR:
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qemu_log_mask(LOG_GUEST_ERROR,
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"SSE MHU: read of write-only register at offset 0x%x\n",
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(int)offset);
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r = 0;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"SSE MHU read: bad offset 0x%x\n", (int)offset);
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r = 0;
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break;
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}
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trace_armsse_mhu_read(offset, r, size);
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return r;
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}
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static void armsse_mhu_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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ARMSSEMHU *s = ARMSSE_MHU(opaque);
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trace_armsse_mhu_write(offset, value, size);
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switch (offset) {
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case A_CPU0INTR_SET:
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s->cpu0intr |= (value & INTR_MASK);
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break;
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case A_CPU0INTR_CLR:
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s->cpu0intr &= ~(value & INTR_MASK);
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break;
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case A_CPU1INTR_SET:
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s->cpu1intr |= (value & INTR_MASK);
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break;
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case A_CPU1INTR_CLR:
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s->cpu1intr &= ~(value & INTR_MASK);
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break;
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case A_CPU0INTR_STAT:
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case A_CPU1INTR_STAT:
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case A_PID4 ... A_CID3:
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qemu_log_mask(LOG_GUEST_ERROR,
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"SSE MHU: write to read-only register at offset 0x%x\n",
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(int)offset);
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"SSE MHU write: bad offset 0x%x\n", (int)offset);
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break;
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}
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armsse_mhu_update(s);
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}
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static const MemoryRegionOps armsse_mhu_ops = {
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.read = armsse_mhu_read,
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.write = armsse_mhu_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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};
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static void armsse_mhu_reset(DeviceState *dev)
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{
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ARMSSEMHU *s = ARMSSE_MHU(dev);
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s->cpu0intr = 0;
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s->cpu1intr = 0;
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}
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static const VMStateDescription armsse_mhu_vmstate = {
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.name = "armsse-mhu",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(cpu0intr, ARMSSEMHU),
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VMSTATE_UINT32(cpu1intr, ARMSSEMHU),
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VMSTATE_END_OF_LIST()
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},
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};
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static void armsse_mhu_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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ARMSSEMHU *s = ARMSSE_MHU(obj);
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memory_region_init_io(&s->iomem, obj, &armsse_mhu_ops,
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s, "armsse-mhu", 0x1000);
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sysbus_init_mmio(sbd, &s->iomem);
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sysbus_init_irq(sbd, &s->cpu0irq);
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sysbus_init_irq(sbd, &s->cpu1irq);
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}
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static void armsse_mhu_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = armsse_mhu_reset;
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dc->vmsd = &armsse_mhu_vmstate;
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}
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static const TypeInfo armsse_mhu_info = {
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.name = TYPE_ARMSSE_MHU,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(ARMSSEMHU),
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.instance_init = armsse_mhu_init,
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.class_init = armsse_mhu_class_init,
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};
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static void armsse_mhu_register_types(void)
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{
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type_register_static(&armsse_mhu_info);
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}
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type_init(armsse_mhu_register_types);
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