qemu-patch-raspberry4/hw/riscv
Markus Armbruster 118bfd76c9 qdev: Use returned bool to check for qdev_realize() etc. failure
Convert

    foo(..., &err);
    if (err) {
        ...
    }

to

    if (!foo(..., &err)) {
        ...
    }

for qdev_realize(), qdev_realize_and_unref(), qbus_realize() and their
wrappers isa_realize_and_unref(), pci_realize_and_unref(),
sysbus_realize(), sysbus_realize_and_unref(), usb_realize_and_unref().
Coccinelle script:

    @@
    identifier fun = {
        isa_realize_and_unref, pci_realize_and_unref, qbus_realize,
        qdev_realize, qdev_realize_and_unref, sysbus_realize,
        sysbus_realize_and_unref, usb_realize_and_unref
    };
    expression list args, args2;
    typedef Error;
    Error *err;
    @@
    -    fun(args, &err, args2);
    -    if (err)
    +    if (!fun(args, &err, args2))
         {
             ...
         }

Chokes on hw/arm/musicpal.c's lcd_refresh() with the unhelpful error
message "no position information".  Nothing to convert there; skipped.

Fails to convert hw/arm/armsse.c, because Coccinelle gets confused by
ARMSSE being used both as typedef and function-like macro there.
Converted manually.

A few line breaks tidied up manually.

Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
Message-Id: <20200707160613.848843-5-armbru@redhat.com>
2020-07-10 15:01:06 +02:00
..
boot.c riscv: Change the default behavior if no -bios option is specified 2020-06-03 09:11:51 -07:00
Kconfig hw/char: Initial commit of Ibex UART 2020-06-19 08:24:07 -07:00
Makefile.objs riscv: Initial commit of OpenTitan machine 2020-06-03 09:11:51 -07:00
opentitan.c qdev: Use returned bool to check for qdev_realize() etc. failure 2020-07-10 15:01:06 +02:00
riscv_hart.c riscv_hart: Fix riscv_harts_realize() error API violations 2020-07-02 06:25:29 +02:00
riscv_htif.c chardev: Use QEMUChrEvent enum in IOEventHandler typedef 2020-01-08 11:15:35 +01:00
sifive_clint.c hw/riscv: Allow 64 bit access to SiFive CLINT 2020-07-02 09:19:32 -07:00
sifive_e.c qdev: Use returned bool to check for qdev_realize() etc. failure 2020-07-10 15:01:06 +02:00
sifive_e_prci.c sysbus: Convert to sysbus_realize() etc. with Coccinelle 2020-06-15 22:05:28 +02:00
sifive_gpio.c hw/riscv: sifive_gpio: Do not blindly trigger output IRQs 2020-06-19 08:25:27 -07:00
sifive_plic.c riscv: plic: Add a couple of mising sifive_plic_update calls 2020-07-02 09:19:32 -07:00
sifive_test.c sysbus: Convert to sysbus_realize() etc. with Coccinelle 2020-06-15 22:05:28 +02:00
sifive_u.c qdev: Use returned bool to check for qdev_realize() etc. failure 2020-07-10 15:01:06 +02:00
sifive_u_otp.c qdev: set properties with device_class_set_props() 2020-01-24 20:59:15 +01:00
sifive_u_prci.c riscv: sifive: Implement PRCI model for FU540 2019-09-17 08:42:47 -07:00
sifive_uart.c chardev: Use QEMUChrEvent enum in IOEventHandler typedef 2020-01-08 11:15:35 +01:00
spike.c sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 1 2020-06-15 22:06:04 +02:00
trace-events SiFive RISC-V GPIO Device 2019-05-24 11:58:30 -07:00
virt.c sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 1 2020-06-15 22:06:04 +02:00