It is a common thing amongst the various cpu reset functions want to flush the SoftMMU's TLB entries. This is done either by calling tlb_flush directly or by way of a general memset of the CPU structure (sometimes both). This moves the tlb_flush call to the common reset function and additionally ensures it is only done for the CONFIG_SOFTMMU case and when tcg is enabled. In some target cases we add an empty end_of_reset_fields structure to the target vCPU structure so have a clear end point for any memset which is resetting value in the structure before CPU_COMMON (where the TLB structures are). While this is a nice clean-up in general it is also a precursor for changes coming to cputlb for MTTCG where the clearing of entries can't be done arbitrarily across vCPUs. Currently the cpu_reset function is usually called from the context of another vCPU as the architectural power up sequence is run. By using the cputlb API functions we can ensure the right behaviour in the future. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
292 lines
8.5 KiB
C
292 lines
8.5 KiB
C
/*
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* QEMU MicroBlaze CPU
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*
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* Copyright (c) 2009 Edgar E. Iglesias
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* Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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* Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "qemu-common.h"
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#include "hw/qdev-properties.h"
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#include "migration/vmstate.h"
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#include "exec/exec-all.h"
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static const struct {
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const char *name;
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uint8_t version_id;
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} mb_cpu_lookup[] = {
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/* These key value are as per MBV field in PVR0 */
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{"5.00.a", 0x01},
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{"5.00.b", 0x02},
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{"5.00.c", 0x03},
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{"6.00.a", 0x04},
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{"6.00.b", 0x06},
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{"7.00.a", 0x05},
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{"7.00.b", 0x07},
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{"7.10.a", 0x08},
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{"7.10.b", 0x09},
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{"7.10.c", 0x0a},
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{"7.10.d", 0x0b},
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{"7.20.a", 0x0c},
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{"7.20.b", 0x0d},
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{"7.20.c", 0x0e},
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{"7.20.d", 0x0f},
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{"7.30.a", 0x10},
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{"7.30.b", 0x11},
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{"8.00.a", 0x12},
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{"8.00.b", 0x13},
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{"8.10.a", 0x14},
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{"8.20.a", 0x15},
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{"8.20.b", 0x16},
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{"8.30.a", 0x17},
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{"8.40.a", 0x18},
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{"8.40.b", 0x19},
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{"8.50.a", 0x1A},
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{"9.0", 0x1B},
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{"9.1", 0x1D},
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{"9.2", 0x1F},
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{"9.3", 0x20},
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{NULL, 0},
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};
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static void mb_cpu_set_pc(CPUState *cs, vaddr value)
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{
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MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
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cpu->env.sregs[SR_PC] = value;
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}
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static bool mb_cpu_has_work(CPUState *cs)
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{
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return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
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}
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#ifndef CONFIG_USER_ONLY
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static void microblaze_cpu_set_irq(void *opaque, int irq, int level)
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{
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MicroBlazeCPU *cpu = opaque;
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CPUState *cs = CPU(cpu);
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int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;
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if (level) {
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cpu_interrupt(cs, type);
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} else {
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cpu_reset_interrupt(cs, type);
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}
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}
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#endif
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/* CPUClass::reset() */
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static void mb_cpu_reset(CPUState *s)
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{
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MicroBlazeCPU *cpu = MICROBLAZE_CPU(s);
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MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu);
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CPUMBState *env = &cpu->env;
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mcc->parent_reset(s);
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memset(env, 0, offsetof(CPUMBState, end_reset_fields));
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env->res_addr = RES_ADDR_NONE;
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/* Disable stack protector. */
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env->shr = ~0;
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env->sregs[SR_PC] = cpu->cfg.base_vectors;
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#if defined(CONFIG_USER_ONLY)
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/* start in user mode with interrupts enabled. */
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env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM;
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#else
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env->sregs[SR_MSR] = 0;
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mmu_init(&env->mmu);
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env->mmu.c_mmu = 3;
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env->mmu.c_mmu_tlb_access = 3;
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env->mmu.c_mmu_zones = 16;
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#endif
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}
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static void mb_disas_set_info(CPUState *cpu, disassemble_info *info)
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{
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info->mach = bfd_arch_microblaze;
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info->print_insn = print_insn_microblaze;
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}
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static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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CPUState *cs = CPU(dev);
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MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
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MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
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CPUMBState *env = &cpu->env;
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uint8_t version_code = 0;
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int i = 0;
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Error *local_err = NULL;
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cpu_exec_realizefn(cs, &local_err);
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if (local_err != NULL) {
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error_propagate(errp, local_err);
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return;
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}
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qemu_init_vcpu(cs);
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env->pvr.regs[0] = PVR0_USE_BARREL_MASK \
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| PVR0_USE_DIV_MASK \
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| PVR0_USE_HW_MUL_MASK \
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| PVR0_USE_EXC_MASK \
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| PVR0_USE_ICACHE_MASK \
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| PVR0_USE_DCACHE_MASK \
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| (0xb << 8);
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env->pvr.regs[2] = PVR2_D_OPB_MASK \
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| PVR2_D_LMB_MASK \
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| PVR2_I_OPB_MASK \
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| PVR2_I_LMB_MASK \
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| PVR2_USE_MSR_INSTR \
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| PVR2_USE_PCMP_INSTR \
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| PVR2_USE_BARREL_MASK \
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| PVR2_USE_DIV_MASK \
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| PVR2_USE_HW_MUL_MASK \
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| PVR2_USE_MUL64_MASK \
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| PVR2_FPU_EXC_MASK \
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| 0;
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for (i = 0; mb_cpu_lookup[i].name && cpu->cfg.version; i++) {
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if (strcmp(mb_cpu_lookup[i].name, cpu->cfg.version) == 0) {
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version_code = mb_cpu_lookup[i].version_id;
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break;
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}
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}
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if (!version_code) {
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qemu_log("Invalid MicroBlaze version number: %s\n", cpu->cfg.version);
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}
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env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
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(cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
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(cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) |
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(cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
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(version_code << 16) |
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(cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0);
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env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
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(cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0);
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env->pvr.regs[5] |= cpu->cfg.dcache_writeback ?
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PVR5_DCACHE_WRITEBACK_MASK : 0;
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env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */
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env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
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mcc->parent_realize(dev, errp);
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}
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static void mb_cpu_initfn(Object *obj)
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{
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CPUState *cs = CPU(obj);
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MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj);
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CPUMBState *env = &cpu->env;
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static bool tcg_initialized;
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cs->env_ptr = env;
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set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
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#ifndef CONFIG_USER_ONLY
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/* Inbound IRQ and FIR lines */
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qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2);
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#endif
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if (tcg_enabled() && !tcg_initialized) {
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tcg_initialized = true;
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mb_tcg_init();
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}
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}
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static const VMStateDescription vmstate_mb_cpu = {
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.name = "cpu",
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.unmigratable = 1,
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};
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static Property mb_properties[] = {
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DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0),
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DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot,
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false),
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/* If use-fpu > 0 - FPU is enabled
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* If use-fpu = 2 - Floating point conversion and square root instructions
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* are enabled
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*/
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DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2),
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DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
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DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
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false),
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DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
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DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
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DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void mb_cpu_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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CPUClass *cc = CPU_CLASS(oc);
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MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc);
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mcc->parent_realize = dc->realize;
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dc->realize = mb_cpu_realizefn;
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mcc->parent_reset = cc->reset;
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cc->reset = mb_cpu_reset;
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cc->has_work = mb_cpu_has_work;
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cc->do_interrupt = mb_cpu_do_interrupt;
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cc->cpu_exec_interrupt = mb_cpu_exec_interrupt;
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cc->dump_state = mb_cpu_dump_state;
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cc->set_pc = mb_cpu_set_pc;
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cc->gdb_read_register = mb_cpu_gdb_read_register;
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cc->gdb_write_register = mb_cpu_gdb_write_register;
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#ifdef CONFIG_USER_ONLY
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cc->handle_mmu_fault = mb_cpu_handle_mmu_fault;
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#else
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cc->do_unassigned_access = mb_cpu_unassigned_access;
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cc->get_phys_page_debug = mb_cpu_get_phys_page_debug;
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#endif
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dc->vmsd = &vmstate_mb_cpu;
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dc->props = mb_properties;
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cc->gdb_num_core_regs = 32 + 5;
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cc->disas_set_info = mb_disas_set_info;
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}
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static const TypeInfo mb_cpu_type_info = {
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.name = TYPE_MICROBLAZE_CPU,
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.parent = TYPE_CPU,
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.instance_size = sizeof(MicroBlazeCPU),
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.instance_init = mb_cpu_initfn,
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.class_size = sizeof(MicroBlazeCPUClass),
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.class_init = mb_cpu_class_init,
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};
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static void mb_cpu_register_types(void)
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{
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type_register_static(&mb_cpu_type_info);
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}
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type_init(mb_cpu_register_types)
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