At the moment the only POWER9 model which is listed in qemu is v1.0 (aka "DD1"). This is a very early (read, buggy) version which will never be released to the public - it was included in qemu only for the convenience of those doing bringup on the early silicon. For bonus points, we actually had its PVR incorrect in the table (0x004e0000 instead of 0x004e0100). We also never actually implemented the differences in behaviour (read, bugs) that marked DD1 in qemu. Now that we know the PVR for the substantially better v2.0 (DD2) chip, include it and make it the default POWER9 in qemu. For the time being we leave the DD1 definition in place for the poor souls (read, me) who still need to work with DD1 hardware. Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
349 lines
9.4 KiB
C
349 lines
9.4 KiB
C
/*
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* sPAPR CPU core device, acts as container of CPU thread devices.
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*
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* Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "hw/cpu/core.h"
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#include "hw/ppc/spapr_cpu_core.h"
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#include "target/ppc/cpu.h"
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#include "hw/ppc/spapr.h"
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#include "hw/boards.h"
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#include "qapi/error.h"
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#include "sysemu/cpus.h"
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#include "sysemu/kvm.h"
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#include "target/ppc/kvm_ppc.h"
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#include "hw/ppc/ppc.h"
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#include "target/ppc/mmu-hash64.h"
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#include "sysemu/numa.h"
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#include "sysemu/hw_accel.h"
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#include "qemu/error-report.h"
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void spapr_cpu_parse_features(sPAPRMachineState *spapr)
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{
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/*
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* Backwards compatibility hack:
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*
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* CPUs had a "compat=" property which didn't make sense for
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* anything except pseries. It was replaced by "max-cpu-compat"
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* machine option. This supports old command lines like
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* -cpu POWER8,compat=power7
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* By stripping the compat option and applying it to the machine
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* before passing it on to the cpu level parser.
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*/
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gchar **inpieces;
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int i, j;
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gchar *compat_str = NULL;
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inpieces = g_strsplit(MACHINE(spapr)->cpu_model, ",", 0);
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/* inpieces[0] is the actual model string */
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i = 1;
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j = 1;
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while (inpieces[i]) {
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if (g_str_has_prefix(inpieces[i], "compat=")) {
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/* in case of multiple compat= options */
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g_free(compat_str);
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compat_str = inpieces[i];
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} else {
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j++;
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}
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i++;
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/* Excise compat options from list */
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inpieces[j] = inpieces[i];
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}
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if (compat_str) {
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char *val = compat_str + strlen("compat=");
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gchar *newprops = g_strjoinv(",", inpieces);
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object_property_set_str(OBJECT(spapr), val, "max-cpu-compat",
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&error_fatal);
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ppc_cpu_parse_features(newprops);
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g_free(newprops);
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} else {
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ppc_cpu_parse_features(MACHINE(spapr)->cpu_model);
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}
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g_strfreev(inpieces);
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}
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static void spapr_cpu_reset(void *opaque)
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{
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PowerPCCPU *cpu = opaque;
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CPUState *cs = CPU(cpu);
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CPUPPCState *env = &cpu->env;
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cpu_reset(cs);
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/* All CPUs start halted. CPU0 is unhalted from the machine level
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* reset code and the rest are explicitly started up by the guest
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* using an RTAS call */
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cs->halted = 1;
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env->spr[SPR_HIOR] = 0;
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}
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static void spapr_cpu_destroy(PowerPCCPU *cpu)
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{
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qemu_unregister_reset(spapr_cpu_reset, cpu);
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}
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static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu,
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Error **errp)
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{
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CPUPPCState *env = &cpu->env;
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/* Set time-base frequency to 512 MHz */
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cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ);
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/* Enable PAPR mode in TCG or KVM */
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cpu_ppc_set_papr(cpu, PPC_VIRTUAL_HYPERVISOR(spapr));
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qemu_register_reset(spapr_cpu_reset, cpu);
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spapr_cpu_reset(cpu);
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}
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/*
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* Return the sPAPR CPU core type for @model which essentially is the CPU
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* model specified with -cpu cmdline option.
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*/
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char *spapr_get_cpu_core_type(const char *model)
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{
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char *core_type;
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gchar **model_pieces = g_strsplit(model, ",", 2);
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gchar *cpu_model = g_ascii_strdown(model_pieces[0], -1);
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g_strfreev(model_pieces);
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core_type = g_strdup_printf("%s-" TYPE_SPAPR_CPU_CORE, cpu_model);
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/* Check whether it exists or whether we have to look up an alias name */
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if (!object_class_by_name(core_type)) {
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const char *realmodel;
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g_free(core_type);
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core_type = NULL;
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realmodel = ppc_cpu_lookup_alias(cpu_model);
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if (realmodel) {
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core_type = spapr_get_cpu_core_type(realmodel);
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}
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}
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g_free(cpu_model);
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return core_type;
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}
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static void spapr_cpu_core_unrealizefn(DeviceState *dev, Error **errp)
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{
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sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
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sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(dev));
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const char *typename = object_class_get_name(scc->cpu_class);
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size_t size = object_type_get_instance_size(typename);
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CPUCore *cc = CPU_CORE(dev);
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int i;
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for (i = 0; i < cc->nr_threads; i++) {
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void *obj = sc->threads + i * size;
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DeviceState *dev = DEVICE(obj);
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CPUState *cs = CPU(dev);
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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spapr_cpu_destroy(cpu);
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object_unparent(cpu->intc);
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cpu_remove_sync(cs);
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object_unparent(obj);
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}
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g_free(sc->threads);
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}
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static void spapr_cpu_core_realize_child(Object *child,
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sPAPRMachineState *spapr, Error **errp)
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{
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Error *local_err = NULL;
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CPUState *cs = CPU(child);
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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Object *obj;
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object_property_set_bool(child, true, "realized", &local_err);
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if (local_err) {
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goto error;
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}
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spapr_cpu_init(spapr, cpu, &local_err);
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if (local_err) {
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goto error;
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}
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obj = object_new(spapr->icp_type);
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object_property_add_child(child, "icp", obj, &error_abort);
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object_unref(obj);
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object_property_add_const_link(obj, ICP_PROP_XICS, OBJECT(spapr),
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&error_abort);
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object_property_add_const_link(obj, ICP_PROP_CPU, child, &error_abort);
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object_property_set_bool(obj, true, "realized", &local_err);
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if (local_err) {
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goto free_icp;
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}
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return;
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free_icp:
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object_unparent(obj);
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error:
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error_propagate(errp, local_err);
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}
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static void spapr_cpu_core_realize(DeviceState *dev, Error **errp)
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{
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sPAPRMachineState *spapr;
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sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
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sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(dev));
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CPUCore *cc = CPU_CORE(OBJECT(dev));
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const char *typename = object_class_get_name(scc->cpu_class);
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size_t size = object_type_get_instance_size(typename);
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Error *local_err = NULL;
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void *obj;
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int i, j;
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spapr = (sPAPRMachineState *) qdev_get_machine();
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if (!object_dynamic_cast((Object *) spapr, TYPE_SPAPR_MACHINE)) {
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error_setg(errp, "spapr-cpu-core needs a pseries machine");
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return;
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}
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sc->threads = g_malloc0(size * cc->nr_threads);
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for (i = 0; i < cc->nr_threads; i++) {
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char id[32];
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CPUState *cs;
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PowerPCCPU *cpu;
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obj = sc->threads + i * size;
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object_initialize(obj, size, typename);
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cs = CPU(obj);
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cpu = POWERPC_CPU(cs);
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cs->cpu_index = cc->core_id + i;
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cpu->vcpu_id = (cc->core_id * spapr->vsmt / smp_threads) + i;
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if (kvm_enabled() && !kvm_vcpu_id_is_valid(cpu->vcpu_id)) {
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error_setg(&local_err, "Can't create CPU with id %d in KVM",
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cpu->vcpu_id);
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error_append_hint(&local_err, "Adjust the number of cpus to %d "
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"or try to raise the number of threads per core\n",
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cpu->vcpu_id * smp_threads / spapr->vsmt);
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goto err;
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}
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/* Set NUMA node for the threads belonged to core */
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cpu->node_id = sc->node_id;
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snprintf(id, sizeof(id), "thread[%d]", i);
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object_property_add_child(OBJECT(sc), id, obj, &local_err);
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if (local_err) {
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goto err;
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}
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object_unref(obj);
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}
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for (j = 0; j < cc->nr_threads; j++) {
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obj = sc->threads + j * size;
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spapr_cpu_core_realize_child(obj, spapr, &local_err);
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if (local_err) {
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goto err;
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}
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}
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return;
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err:
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while (--i >= 0) {
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obj = sc->threads + i * size;
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object_unparent(obj);
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}
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g_free(sc->threads);
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error_propagate(errp, local_err);
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}
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static const char *spapr_core_models[] = {
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/* 970 */
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"970_v2.2",
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/* 970MP variants */
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"970mp_v1.0",
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"970mp_v1.1",
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/* POWER5+ */
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"power5+_v2.1",
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/* POWER7 */
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"power7_v2.3",
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/* POWER7+ */
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"power7+_v2.1",
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/* POWER8 */
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"power8_v2.0",
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/* POWER8E */
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"power8e_v2.1",
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/* POWER8NVL */
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"power8nvl_v1.0",
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/* POWER9 */
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"power9_v1.0",
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"power9_v2.0",
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};
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static Property spapr_cpu_core_properties[] = {
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DEFINE_PROP_INT32("node-id", sPAPRCPUCore, node_id, CPU_UNSET_NUMA_NODE_ID),
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DEFINE_PROP_END_OF_LIST()
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};
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void spapr_cpu_core_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc);
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dc->realize = spapr_cpu_core_realize;
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dc->unrealize = spapr_cpu_core_unrealizefn;
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dc->props = spapr_cpu_core_properties;
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scc->cpu_class = cpu_class_by_name(TYPE_POWERPC_CPU, data);
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g_assert(scc->cpu_class);
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}
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static const TypeInfo spapr_cpu_core_type_info = {
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.name = TYPE_SPAPR_CPU_CORE,
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.parent = TYPE_CPU_CORE,
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.abstract = true,
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.instance_size = sizeof(sPAPRCPUCore),
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.class_size = sizeof(sPAPRCPUCoreClass),
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};
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static void spapr_cpu_core_register_types(void)
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{
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int i;
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type_register_static(&spapr_cpu_core_type_info);
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for (i = 0; i < ARRAY_SIZE(spapr_core_models); i++) {
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TypeInfo type_info = {
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.parent = TYPE_SPAPR_CPU_CORE,
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.instance_size = sizeof(sPAPRCPUCore),
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.class_init = spapr_cpu_core_class_init,
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.class_data = (void *) spapr_core_models[i],
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};
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type_info.name = g_strdup_printf("%s-" TYPE_SPAPR_CPU_CORE,
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spapr_core_models[i]);
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type_register(&type_info);
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g_free((void *)type_info.name);
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}
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}
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type_init(spapr_cpu_core_register_types)
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