Convert the Neon VDUP (scalar) insn to decodetree. (Note that we can't call this just "VDUP" as we used that already in vfp.decode for the "VDUP (general purpose register" insn.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
530 lines
26 KiB
Plaintext
530 lines
26 KiB
Plaintext
# AArch32 Neon data-processing instruction descriptions
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#
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# Copyright (c) 2020 Linaro, Ltd
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#
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# This library is free software; you can redistribute it and/or
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# modify it under the terms of the GNU Lesser General Public
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# License as published by the Free Software Foundation; either
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# version 2 of the License, or (at your option) any later version.
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#
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# This library is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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# Lesser General Public License for more details.
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#
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# You should have received a copy of the GNU Lesser General Public
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# License along with this library; if not, see <http://www.gnu.org/licenses/>.
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#
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# This file is processed by scripts/decodetree.py
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#
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# VFP/Neon register fields; same as vfp.decode
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%vm_dp 5:1 0:4
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%vn_dp 7:1 16:4
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%vd_dp 22:1 12:4
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# Encodings for Neon data processing instructions where the T32 encoding
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# is a simple transformation of the A32 encoding.
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# More specifically, this file covers instructions where the A32 encoding is
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# 0b1111_001p_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
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# and the T32 encoding is
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# 0b111p_1111_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
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# This file works on the A32 encoding only; calling code for T32 has to
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# transform the insn into the A32 version first.
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######################################################################
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# 3-reg-same grouping:
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# 1111 001 U 0 D sz:2 Vn:4 Vd:4 opc:4 N Q M op Vm:4
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######################################################################
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&3same vm vn vd q size
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@3same .... ... . . . size:2 .... .... .... . q:1 . . .... \
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&3same vm=%vm_dp vn=%vn_dp vd=%vd_dp
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@3same_q0 .... ... . . . size:2 .... .... .... . 0 . . .... \
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&3same vm=%vm_dp vn=%vn_dp vd=%vd_dp q=0
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# For FP insns the high bit of 'size' is used as part of opcode decode
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@3same_fp .... ... . . . . size:1 .... .... .... . q:1 . . .... \
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&3same vm=%vm_dp vn=%vn_dp vd=%vd_dp
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@3same_fp_q0 .... ... . . . . size:1 .... .... .... . 0 . . .... \
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&3same vm=%vm_dp vn=%vn_dp vd=%vd_dp q=0
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VHADD_S_3s 1111 001 0 0 . .. .... .... 0000 . . . 0 .... @3same
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VHADD_U_3s 1111 001 1 0 . .. .... .... 0000 . . . 0 .... @3same
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VQADD_S_3s 1111 001 0 0 . .. .... .... 0000 . . . 1 .... @3same
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VQADD_U_3s 1111 001 1 0 . .. .... .... 0000 . . . 1 .... @3same
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VRHADD_S_3s 1111 001 0 0 . .. .... .... 0001 . . . 0 .... @3same
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VRHADD_U_3s 1111 001 1 0 . .. .... .... 0001 . . . 0 .... @3same
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@3same_logic .... ... . . . .. .... .... .... . q:1 .. .... \
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&3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=0
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VAND_3s 1111 001 0 0 . 00 .... .... 0001 ... 1 .... @3same_logic
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VBIC_3s 1111 001 0 0 . 01 .... .... 0001 ... 1 .... @3same_logic
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VORR_3s 1111 001 0 0 . 10 .... .... 0001 ... 1 .... @3same_logic
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VORN_3s 1111 001 0 0 . 11 .... .... 0001 ... 1 .... @3same_logic
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VEOR_3s 1111 001 1 0 . 00 .... .... 0001 ... 1 .... @3same_logic
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VBSL_3s 1111 001 1 0 . 01 .... .... 0001 ... 1 .... @3same_logic
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VBIT_3s 1111 001 1 0 . 10 .... .... 0001 ... 1 .... @3same_logic
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VBIF_3s 1111 001 1 0 . 11 .... .... 0001 ... 1 .... @3same_logic
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VHSUB_S_3s 1111 001 0 0 . .. .... .... 0010 . . . 0 .... @3same
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VHSUB_U_3s 1111 001 1 0 . .. .... .... 0010 . . . 0 .... @3same
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VQSUB_S_3s 1111 001 0 0 . .. .... .... 0010 . . . 1 .... @3same
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VQSUB_U_3s 1111 001 1 0 . .. .... .... 0010 . . . 1 .... @3same
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VCGT_S_3s 1111 001 0 0 . .. .... .... 0011 . . . 0 .... @3same
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VCGT_U_3s 1111 001 1 0 . .. .... .... 0011 . . . 0 .... @3same
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VCGE_S_3s 1111 001 0 0 . .. .... .... 0011 . . . 1 .... @3same
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VCGE_U_3s 1111 001 1 0 . .. .... .... 0011 . . . 1 .... @3same
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# The _rev suffix indicates that Vn and Vm are reversed. This is
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# the case for shifts. In the Arm ARM these insns are documented
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# with the Vm and Vn fields in their usual places, but in the
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# assembly the operands are listed "backwards", ie in the order
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# Dd, Dm, Dn where other insns use Dd, Dn, Dm. For QEMU we choose
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# to consider Vm and Vn as being in different fields in the insn,
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# which allows us to avoid special-casing shifts in the trans_
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# function code. We would otherwise need to manually swap the operands
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# over to call Neon helper functions that are shared with AArch64,
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# which does not have this odd reversed-operand situation.
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@3same_rev .... ... . . . size:2 .... .... .... . q:1 . . .... \
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&3same vn=%vm_dp vm=%vn_dp vd=%vd_dp
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VSHL_S_3s 1111 001 0 0 . .. .... .... 0100 . . . 0 .... @3same_rev
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VSHL_U_3s 1111 001 1 0 . .. .... .... 0100 . . . 0 .... @3same_rev
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# Insns operating on 64-bit elements (size!=0b11 handled elsewhere)
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# The _rev suffix indicates that Vn and Vm are reversed (as explained
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# by the comment for the @3same_rev format).
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@3same_64_rev .... ... . . . 11 .... .... .... . q:1 . . .... \
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&3same vm=%vn_dp vn=%vm_dp vd=%vd_dp size=3
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{
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VQSHL_S64_3s 1111 001 0 0 . .. .... .... 0100 . . . 1 .... @3same_64_rev
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VQSHL_S_3s 1111 001 0 0 . .. .... .... 0100 . . . 1 .... @3same_rev
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}
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{
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VQSHL_U64_3s 1111 001 1 0 . .. .... .... 0100 . . . 1 .... @3same_64_rev
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VQSHL_U_3s 1111 001 1 0 . .. .... .... 0100 . . . 1 .... @3same_rev
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}
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{
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VRSHL_S64_3s 1111 001 0 0 . .. .... .... 0101 . . . 0 .... @3same_64_rev
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VRSHL_S_3s 1111 001 0 0 . .. .... .... 0101 . . . 0 .... @3same_rev
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}
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{
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VRSHL_U64_3s 1111 001 1 0 . .. .... .... 0101 . . . 0 .... @3same_64_rev
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VRSHL_U_3s 1111 001 1 0 . .. .... .... 0101 . . . 0 .... @3same_rev
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}
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{
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VQRSHL_S64_3s 1111 001 0 0 . .. .... .... 0101 . . . 1 .... @3same_64_rev
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VQRSHL_S_3s 1111 001 0 0 . .. .... .... 0101 . . . 1 .... @3same_rev
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}
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{
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VQRSHL_U64_3s 1111 001 1 0 . .. .... .... 0101 . . . 1 .... @3same_64_rev
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VQRSHL_U_3s 1111 001 1 0 . .. .... .... 0101 . . . 1 .... @3same_rev
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}
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VMAX_S_3s 1111 001 0 0 . .. .... .... 0110 . . . 0 .... @3same
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VMAX_U_3s 1111 001 1 0 . .. .... .... 0110 . . . 0 .... @3same
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VMIN_S_3s 1111 001 0 0 . .. .... .... 0110 . . . 1 .... @3same
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VMIN_U_3s 1111 001 1 0 . .. .... .... 0110 . . . 1 .... @3same
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VABD_S_3s 1111 001 0 0 . .. .... .... 0111 . . . 0 .... @3same
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VABD_U_3s 1111 001 1 0 . .. .... .... 0111 . . . 0 .... @3same
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VABA_S_3s 1111 001 0 0 . .. .... .... 0111 . . . 1 .... @3same
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VABA_U_3s 1111 001 1 0 . .. .... .... 0111 . . . 1 .... @3same
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VADD_3s 1111 001 0 0 . .. .... .... 1000 . . . 0 .... @3same
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VSUB_3s 1111 001 1 0 . .. .... .... 1000 . . . 0 .... @3same
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VTST_3s 1111 001 0 0 . .. .... .... 1000 . . . 1 .... @3same
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VCEQ_3s 1111 001 1 0 . .. .... .... 1000 . . . 1 .... @3same
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VMLA_3s 1111 001 0 0 . .. .... .... 1001 . . . 0 .... @3same
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VMLS_3s 1111 001 1 0 . .. .... .... 1001 . . . 0 .... @3same
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VMUL_3s 1111 001 0 0 . .. .... .... 1001 . . . 1 .... @3same
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VMUL_p_3s 1111 001 1 0 . .. .... .... 1001 . . . 1 .... @3same
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VPMAX_S_3s 1111 001 0 0 . .. .... .... 1010 . . . 0 .... @3same_q0
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VPMAX_U_3s 1111 001 1 0 . .. .... .... 1010 . . . 0 .... @3same_q0
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VPMIN_S_3s 1111 001 0 0 . .. .... .... 1010 . . . 1 .... @3same_q0
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VPMIN_U_3s 1111 001 1 0 . .. .... .... 1010 . . . 1 .... @3same_q0
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VQDMULH_3s 1111 001 0 0 . .. .... .... 1011 . . . 0 .... @3same
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VQRDMULH_3s 1111 001 1 0 . .. .... .... 1011 . . . 0 .... @3same
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VPADD_3s 1111 001 0 0 . .. .... .... 1011 . . . 1 .... @3same_q0
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VQRDMLAH_3s 1111 001 1 0 . .. .... .... 1011 ... 1 .... @3same
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@3same_crypto .... .... .... .... .... .... .... .... \
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&3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=0 q=1
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SHA1C_3s 1111 001 0 0 . 00 .... .... 1100 . 1 . 0 .... @3same_crypto
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SHA1P_3s 1111 001 0 0 . 01 .... .... 1100 . 1 . 0 .... @3same_crypto
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SHA1M_3s 1111 001 0 0 . 10 .... .... 1100 . 1 . 0 .... @3same_crypto
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SHA1SU0_3s 1111 001 0 0 . 11 .... .... 1100 . 1 . 0 .... @3same_crypto
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SHA256H_3s 1111 001 1 0 . 00 .... .... 1100 . 1 . 0 .... @3same_crypto
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SHA256H2_3s 1111 001 1 0 . 01 .... .... 1100 . 1 . 0 .... @3same_crypto
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SHA256SU1_3s 1111 001 1 0 . 10 .... .... 1100 . 1 . 0 .... @3same_crypto
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VFMA_fp_3s 1111 001 0 0 . 0 . .... .... 1100 ... 1 .... @3same_fp
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VFMS_fp_3s 1111 001 0 0 . 1 . .... .... 1100 ... 1 .... @3same_fp
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VQRDMLSH_3s 1111 001 1 0 . .. .... .... 1100 ... 1 .... @3same
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VADD_fp_3s 1111 001 0 0 . 0 . .... .... 1101 ... 0 .... @3same_fp
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VSUB_fp_3s 1111 001 0 0 . 1 . .... .... 1101 ... 0 .... @3same_fp
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VPADD_fp_3s 1111 001 1 0 . 0 . .... .... 1101 ... 0 .... @3same_fp_q0
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VABD_fp_3s 1111 001 1 0 . 1 . .... .... 1101 ... 0 .... @3same_fp
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VMLA_fp_3s 1111 001 0 0 . 0 . .... .... 1101 ... 1 .... @3same_fp
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VMLS_fp_3s 1111 001 0 0 . 1 . .... .... 1101 ... 1 .... @3same_fp
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VMUL_fp_3s 1111 001 1 0 . 0 . .... .... 1101 ... 1 .... @3same_fp
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VCEQ_fp_3s 1111 001 0 0 . 0 . .... .... 1110 ... 0 .... @3same_fp
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VCGE_fp_3s 1111 001 1 0 . 0 . .... .... 1110 ... 0 .... @3same_fp
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VACGE_fp_3s 1111 001 1 0 . 0 . .... .... 1110 ... 1 .... @3same_fp
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VCGT_fp_3s 1111 001 1 0 . 1 . .... .... 1110 ... 0 .... @3same_fp
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VACGT_fp_3s 1111 001 1 0 . 1 . .... .... 1110 ... 1 .... @3same_fp
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VMAX_fp_3s 1111 001 0 0 . 0 . .... .... 1111 ... 0 .... @3same_fp
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VMIN_fp_3s 1111 001 0 0 . 1 . .... .... 1111 ... 0 .... @3same_fp
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VPMAX_fp_3s 1111 001 1 0 . 0 . .... .... 1111 ... 0 .... @3same_fp_q0
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VPMIN_fp_3s 1111 001 1 0 . 1 . .... .... 1111 ... 0 .... @3same_fp_q0
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VRECPS_fp_3s 1111 001 0 0 . 0 . .... .... 1111 ... 1 .... @3same_fp
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VRSQRTS_fp_3s 1111 001 0 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
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VMAXNM_fp_3s 1111 001 1 0 . 0 . .... .... 1111 ... 1 .... @3same_fp
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VMINNM_fp_3s 1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
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######################################################################
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# 2-reg-and-shift grouping:
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# 1111 001 U 1 D immH:3 immL:3 Vd:4 opc:4 L Q M 1 Vm:4
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######################################################################
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&2reg_shift vm vd q shift size
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# Right shifts are encoded as N - shift, where N is the element size in bits.
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%neon_rshift_i6 16:6 !function=rsub_64
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%neon_rshift_i5 16:5 !function=rsub_32
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%neon_rshift_i4 16:4 !function=rsub_16
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%neon_rshift_i3 16:3 !function=rsub_8
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@2reg_shr_d .... ... . . . ...... .... .... 1 q:1 . . .... \
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&2reg_shift vm=%vm_dp vd=%vd_dp size=3 shift=%neon_rshift_i6
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@2reg_shr_s .... ... . . . 1 ..... .... .... 0 q:1 . . .... \
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&2reg_shift vm=%vm_dp vd=%vd_dp size=2 shift=%neon_rshift_i5
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@2reg_shr_h .... ... . . . 01 .... .... .... 0 q:1 . . .... \
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&2reg_shift vm=%vm_dp vd=%vd_dp size=1 shift=%neon_rshift_i4
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@2reg_shr_b .... ... . . . 001 ... .... .... 0 q:1 . . .... \
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&2reg_shift vm=%vm_dp vd=%vd_dp size=0 shift=%neon_rshift_i3
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@2reg_shl_d .... ... . . . shift:6 .... .... 1 q:1 . . .... \
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&2reg_shift vm=%vm_dp vd=%vd_dp size=3
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@2reg_shl_s .... ... . . . 1 shift:5 .... .... 0 q:1 . . .... \
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&2reg_shift vm=%vm_dp vd=%vd_dp size=2
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@2reg_shl_h .... ... . . . 01 shift:4 .... .... 0 q:1 . . .... \
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&2reg_shift vm=%vm_dp vd=%vd_dp size=1
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@2reg_shl_b .... ... . . . 001 shift:3 .... .... 0 q:1 . . .... \
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&2reg_shift vm=%vm_dp vd=%vd_dp size=0
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# Narrowing right shifts: here the Q bit is part of the opcode decode
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@2reg_shrn_d .... ... . . . 1 ..... .... .... 0 . . . .... \
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&2reg_shift vm=%vm_dp vd=%vd_dp size=3 q=0 \
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shift=%neon_rshift_i5
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@2reg_shrn_s .... ... . . . 01 .... .... .... 0 . . . .... \
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&2reg_shift vm=%vm_dp vd=%vd_dp size=2 q=0 \
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shift=%neon_rshift_i4
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@2reg_shrn_h .... ... . . . 001 ... .... .... 0 . . . .... \
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&2reg_shift vm=%vm_dp vd=%vd_dp size=1 q=0 \
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shift=%neon_rshift_i3
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# Long left shifts: again Q is part of opcode decode
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@2reg_shll_s .... ... . . . 1 shift:5 .... .... 0 . . . .... \
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&2reg_shift vm=%vm_dp vd=%vd_dp size=2 q=0
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@2reg_shll_h .... ... . . . 01 shift:4 .... .... 0 . . . .... \
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&2reg_shift vm=%vm_dp vd=%vd_dp size=1 q=0
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@2reg_shll_b .... ... . . . 001 shift:3 .... .... 0 . . . .... \
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&2reg_shift vm=%vm_dp vd=%vd_dp size=0 q=0
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# We use size=0 for fp32 and size=1 for fp16 to match the 3-same encodings.
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@2reg_vcvt .... ... . . . 1 ..... .... .... . q:1 . . .... \
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&2reg_shift vm=%vm_dp vd=%vd_dp size=0 shift=%neon_rshift_i5
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VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d
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VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s
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VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h
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VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_b
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VSHR_U_2sh 1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d
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VSHR_U_2sh 1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s
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VSHR_U_2sh 1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h
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VSHR_U_2sh 1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_b
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VSRA_S_2sh 1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_d
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VSRA_S_2sh 1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_s
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VSRA_S_2sh 1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_h
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VSRA_S_2sh 1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_b
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VSRA_U_2sh 1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_d
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VSRA_U_2sh 1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_s
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VSRA_U_2sh 1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_h
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VSRA_U_2sh 1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_b
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VRSHR_S_2sh 1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_d
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VRSHR_S_2sh 1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_s
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VRSHR_S_2sh 1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_h
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VRSHR_S_2sh 1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_b
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VRSHR_U_2sh 1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_d
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VRSHR_U_2sh 1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_s
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VRSHR_U_2sh 1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_h
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VRSHR_U_2sh 1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_b
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VRSRA_S_2sh 1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_d
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VRSRA_S_2sh 1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_s
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VRSRA_S_2sh 1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_h
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VRSRA_S_2sh 1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_b
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VRSRA_U_2sh 1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_d
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VRSRA_U_2sh 1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_s
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VRSRA_U_2sh 1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_h
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VRSRA_U_2sh 1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_b
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VSRI_2sh 1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_d
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VSRI_2sh 1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_s
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VSRI_2sh 1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_h
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VSRI_2sh 1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_b
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VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_d
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VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s
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VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h
|
|
VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_b
|
|
|
|
VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_d
|
|
VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s
|
|
VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h
|
|
VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_b
|
|
|
|
VQSHLU_64_2sh 1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_d
|
|
VQSHLU_2sh 1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_s
|
|
VQSHLU_2sh 1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_h
|
|
VQSHLU_2sh 1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_b
|
|
|
|
VQSHL_S_64_2sh 1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_d
|
|
VQSHL_S_2sh 1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_s
|
|
VQSHL_S_2sh 1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_h
|
|
VQSHL_S_2sh 1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_b
|
|
|
|
VQSHL_U_64_2sh 1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_d
|
|
VQSHL_U_2sh 1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_s
|
|
VQSHL_U_2sh 1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_h
|
|
VQSHL_U_2sh 1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_b
|
|
|
|
VSHRN_64_2sh 1111 001 0 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_d
|
|
VSHRN_32_2sh 1111 001 0 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_s
|
|
VSHRN_16_2sh 1111 001 0 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_h
|
|
|
|
VRSHRN_64_2sh 1111 001 0 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_d
|
|
VRSHRN_32_2sh 1111 001 0 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_s
|
|
VRSHRN_16_2sh 1111 001 0 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_h
|
|
|
|
VQSHRUN_64_2sh 1111 001 1 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_d
|
|
VQSHRUN_32_2sh 1111 001 1 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_s
|
|
VQSHRUN_16_2sh 1111 001 1 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_h
|
|
|
|
VQRSHRUN_64_2sh 1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_d
|
|
VQRSHRUN_32_2sh 1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_s
|
|
VQRSHRUN_16_2sh 1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_h
|
|
|
|
# VQSHRN with signed input
|
|
VQSHRN_S64_2sh 1111 001 0 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_d
|
|
VQSHRN_S32_2sh 1111 001 0 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_s
|
|
VQSHRN_S16_2sh 1111 001 0 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_h
|
|
|
|
# VQRSHRN with signed input
|
|
VQRSHRN_S64_2sh 1111 001 0 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_d
|
|
VQRSHRN_S32_2sh 1111 001 0 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_s
|
|
VQRSHRN_S16_2sh 1111 001 0 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_h
|
|
|
|
# VQSHRN with unsigned input
|
|
VQSHRN_U64_2sh 1111 001 1 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_d
|
|
VQSHRN_U32_2sh 1111 001 1 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_s
|
|
VQSHRN_U16_2sh 1111 001 1 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_h
|
|
|
|
# VQRSHRN with unsigned input
|
|
VQRSHRN_U64_2sh 1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_d
|
|
VQRSHRN_U32_2sh 1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_s
|
|
VQRSHRN_U16_2sh 1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_h
|
|
|
|
VSHLL_S_2sh 1111 001 0 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_s
|
|
VSHLL_S_2sh 1111 001 0 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_h
|
|
VSHLL_S_2sh 1111 001 0 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_b
|
|
|
|
VSHLL_U_2sh 1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_s
|
|
VSHLL_U_2sh 1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_h
|
|
VSHLL_U_2sh 1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_b
|
|
|
|
# VCVT fixed<->float conversions
|
|
# TODO: FP16 fixed<->float conversions are opc==0b1100 and 0b1101
|
|
VCVT_SF_2sh 1111 001 0 1 . ...... .... 1110 0 . . 1 .... @2reg_vcvt
|
|
VCVT_UF_2sh 1111 001 1 1 . ...... .... 1110 0 . . 1 .... @2reg_vcvt
|
|
VCVT_FS_2sh 1111 001 0 1 . ...... .... 1111 0 . . 1 .... @2reg_vcvt
|
|
VCVT_FU_2sh 1111 001 1 1 . ...... .... 1111 0 . . 1 .... @2reg_vcvt
|
|
|
|
######################################################################
|
|
# 1-reg-and-modified-immediate grouping:
|
|
# 1111 001 i 1 D 000 imm:3 Vd:4 cmode:4 0 Q op 1 Vm:4
|
|
######################################################################
|
|
|
|
&1reg_imm vd q imm cmode op
|
|
|
|
%asimd_imm_value 24:1 16:3 0:4
|
|
|
|
@1reg_imm .... ... . . . ... ... .... .... . q:1 . . .... \
|
|
&1reg_imm imm=%asimd_imm_value vd=%vd_dp
|
|
|
|
# The cmode/op bits here decode VORR/VBIC/VMOV/VMNV, but
|
|
# not in a way we can conveniently represent in decodetree without
|
|
# a lot of repetition:
|
|
# VORR: op=0, (cmode & 1) && cmode < 12
|
|
# VBIC: op=1, (cmode & 1) && cmode < 12
|
|
# VMOV: everything else
|
|
# So we have a single decode line and check the cmode/op in the
|
|
# trans function.
|
|
Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
|
|
|
|
######################################################################
|
|
# Within the "two registers, or three registers of different lengths"
|
|
# grouping ([23,4]=0b10), bits [21:20] are either part of the opcode
|
|
# decode: 0b11 for VEXT, two-reg-misc, VTBL, and duplicate-scalar;
|
|
# or they are a size field for the three-reg-different-lengths and
|
|
# two-reg-and-scalar insn groups (where size cannot be 0b11). This
|
|
# is slightly awkward for decodetree: we handle it with this
|
|
# non-exclusive group which contains within it two exclusive groups:
|
|
# one for the size=0b11 patterns, and one for the size-not-0b11
|
|
# patterns. This allows us to check that none of the insns within
|
|
# each subgroup accidentally overlap each other. Note that all the
|
|
# trans functions for the size-not-0b11 patterns must check and
|
|
# return false for size==3.
|
|
######################################################################
|
|
{
|
|
[
|
|
##################################################################
|
|
# Miscellaneous size=0b11 insns
|
|
##################################################################
|
|
VEXT 1111 001 0 1 . 11 .... .... imm:4 . q:1 . 0 .... \
|
|
vm=%vm_dp vn=%vn_dp vd=%vd_dp
|
|
|
|
VTBL 1111 001 1 1 . 11 .... .... 10 len:2 . op:1 . 0 .... \
|
|
vm=%vm_dp vn=%vn_dp vd=%vd_dp
|
|
|
|
VDUP_scalar 1111 001 1 1 . 11 index:3 1 .... 11 000 q:1 . 0 .... \
|
|
vm=%vm_dp vd=%vd_dp size=0
|
|
VDUP_scalar 1111 001 1 1 . 11 index:2 10 .... 11 000 q:1 . 0 .... \
|
|
vm=%vm_dp vd=%vd_dp size=1
|
|
VDUP_scalar 1111 001 1 1 . 11 index:1 100 .... 11 000 q:1 . 0 .... \
|
|
vm=%vm_dp vd=%vd_dp size=2
|
|
]
|
|
|
|
# Subgroup for size != 0b11
|
|
[
|
|
##################################################################
|
|
# 3-reg-different-length grouping:
|
|
# 1111 001 U 1 D sz!=11 Vn:4 Vd:4 opc:4 N 0 M 0 Vm:4
|
|
##################################################################
|
|
|
|
&3diff vm vn vd size
|
|
|
|
@3diff .... ... . . . size:2 .... .... .... . . . . .... \
|
|
&3diff vm=%vm_dp vn=%vn_dp vd=%vd_dp
|
|
|
|
VADDL_S_3d 1111 001 0 1 . .. .... .... 0000 . 0 . 0 .... @3diff
|
|
VADDL_U_3d 1111 001 1 1 . .. .... .... 0000 . 0 . 0 .... @3diff
|
|
|
|
VADDW_S_3d 1111 001 0 1 . .. .... .... 0001 . 0 . 0 .... @3diff
|
|
VADDW_U_3d 1111 001 1 1 . .. .... .... 0001 . 0 . 0 .... @3diff
|
|
|
|
VSUBL_S_3d 1111 001 0 1 . .. .... .... 0010 . 0 . 0 .... @3diff
|
|
VSUBL_U_3d 1111 001 1 1 . .. .... .... 0010 . 0 . 0 .... @3diff
|
|
|
|
VSUBW_S_3d 1111 001 0 1 . .. .... .... 0011 . 0 . 0 .... @3diff
|
|
VSUBW_U_3d 1111 001 1 1 . .. .... .... 0011 . 0 . 0 .... @3diff
|
|
|
|
VADDHN_3d 1111 001 0 1 . .. .... .... 0100 . 0 . 0 .... @3diff
|
|
VRADDHN_3d 1111 001 1 1 . .. .... .... 0100 . 0 . 0 .... @3diff
|
|
|
|
VABAL_S_3d 1111 001 0 1 . .. .... .... 0101 . 0 . 0 .... @3diff
|
|
VABAL_U_3d 1111 001 1 1 . .. .... .... 0101 . 0 . 0 .... @3diff
|
|
|
|
VSUBHN_3d 1111 001 0 1 . .. .... .... 0110 . 0 . 0 .... @3diff
|
|
VRSUBHN_3d 1111 001 1 1 . .. .... .... 0110 . 0 . 0 .... @3diff
|
|
|
|
VABDL_S_3d 1111 001 0 1 . .. .... .... 0111 . 0 . 0 .... @3diff
|
|
VABDL_U_3d 1111 001 1 1 . .. .... .... 0111 . 0 . 0 .... @3diff
|
|
|
|
VMLAL_S_3d 1111 001 0 1 . .. .... .... 1000 . 0 . 0 .... @3diff
|
|
VMLAL_U_3d 1111 001 1 1 . .. .... .... 1000 . 0 . 0 .... @3diff
|
|
|
|
VQDMLAL_3d 1111 001 0 1 . .. .... .... 1001 . 0 . 0 .... @3diff
|
|
|
|
VMLSL_S_3d 1111 001 0 1 . .. .... .... 1010 . 0 . 0 .... @3diff
|
|
VMLSL_U_3d 1111 001 1 1 . .. .... .... 1010 . 0 . 0 .... @3diff
|
|
|
|
VQDMLSL_3d 1111 001 0 1 . .. .... .... 1011 . 0 . 0 .... @3diff
|
|
|
|
VMULL_S_3d 1111 001 0 1 . .. .... .... 1100 . 0 . 0 .... @3diff
|
|
VMULL_U_3d 1111 001 1 1 . .. .... .... 1100 . 0 . 0 .... @3diff
|
|
|
|
VQDMULL_3d 1111 001 0 1 . .. .... .... 1101 . 0 . 0 .... @3diff
|
|
|
|
VMULL_P_3d 1111 001 0 1 . .. .... .... 1110 . 0 . 0 .... @3diff
|
|
|
|
##################################################################
|
|
# 2-regs-plus-scalar grouping:
|
|
# 1111 001 Q 1 D sz!=11 Vn:4 Vd:4 opc:4 N 1 M 0 Vm:4
|
|
##################################################################
|
|
&2scalar vm vn vd size q
|
|
|
|
@2scalar .... ... q:1 . . size:2 .... .... .... . . . . .... \
|
|
&2scalar vm=%vm_dp vn=%vn_dp vd=%vd_dp
|
|
# For the 'long' ops the Q bit is part of insn decode
|
|
@2scalar_q0 .... ... . . . size:2 .... .... .... . . . . .... \
|
|
&2scalar vm=%vm_dp vn=%vn_dp vd=%vd_dp q=0
|
|
|
|
VMLA_2sc 1111 001 . 1 . .. .... .... 0000 . 1 . 0 .... @2scalar
|
|
VMLA_F_2sc 1111 001 . 1 . .. .... .... 0001 . 1 . 0 .... @2scalar
|
|
|
|
VMLAL_S_2sc 1111 001 0 1 . .. .... .... 0010 . 1 . 0 .... @2scalar_q0
|
|
VMLAL_U_2sc 1111 001 1 1 . .. .... .... 0010 . 1 . 0 .... @2scalar_q0
|
|
|
|
VQDMLAL_2sc 1111 001 0 1 . .. .... .... 0011 . 1 . 0 .... @2scalar_q0
|
|
|
|
VMLS_2sc 1111 001 . 1 . .. .... .... 0100 . 1 . 0 .... @2scalar
|
|
VMLS_F_2sc 1111 001 . 1 . .. .... .... 0101 . 1 . 0 .... @2scalar
|
|
|
|
VMLSL_S_2sc 1111 001 0 1 . .. .... .... 0110 . 1 . 0 .... @2scalar_q0
|
|
VMLSL_U_2sc 1111 001 1 1 . .. .... .... 0110 . 1 . 0 .... @2scalar_q0
|
|
|
|
VQDMLSL_2sc 1111 001 0 1 . .. .... .... 0111 . 1 . 0 .... @2scalar_q0
|
|
|
|
VMUL_2sc 1111 001 . 1 . .. .... .... 1000 . 1 . 0 .... @2scalar
|
|
VMUL_F_2sc 1111 001 . 1 . .. .... .... 1001 . 1 . 0 .... @2scalar
|
|
|
|
VMULL_S_2sc 1111 001 0 1 . .. .... .... 1010 . 1 . 0 .... @2scalar_q0
|
|
VMULL_U_2sc 1111 001 1 1 . .. .... .... 1010 . 1 . 0 .... @2scalar_q0
|
|
|
|
VQDMULL_2sc 1111 001 0 1 . .. .... .... 1011 . 1 . 0 .... @2scalar_q0
|
|
|
|
VQDMULH_2sc 1111 001 . 1 . .. .... .... 1100 . 1 . 0 .... @2scalar
|
|
VQRDMULH_2sc 1111 001 . 1 . .. .... .... 1101 . 1 . 0 .... @2scalar
|
|
|
|
VQRDMLAH_2sc 1111 001 . 1 . .. .... .... 1110 . 1 . 0 .... @2scalar
|
|
VQRDMLSH_2sc 1111 001 . 1 . .. .... .... 1111 . 1 . 0 .... @2scalar
|
|
]
|
|
}
|