Mult are generated inline (using a cool trick pointed out by Richard), but for div and rem, given the complexity of the implementation of these instructions, we call helpers to produce their behavior. From an implementation standpoint, the helpers return the low part of the results, while the high part is temporarily stored in a dedicated field of cpu_env that is used to update the architectural register in the generation wrapper. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-15-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
428 lines
12 KiB
C++
428 lines
12 KiB
C++
/*
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* RISC-V translation routines for the RV64M Standard Extension.
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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* Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
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* Bastian Koppelmann, kbastian@mail.uni-paderborn.de
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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static void gen_mulhu_i128(TCGv r2, TCGv r3, TCGv al, TCGv ah, TCGv bl, TCGv bh)
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{
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TCGv tmpl = tcg_temp_new();
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TCGv tmph = tcg_temp_new();
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TCGv r0 = tcg_temp_new();
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TCGv r1 = tcg_temp_new();
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TCGv zero = tcg_constant_tl(0);
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tcg_gen_mulu2_tl(r0, r1, al, bl);
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tcg_gen_mulu2_tl(tmpl, tmph, al, bh);
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tcg_gen_add2_tl(r1, r2, r1, zero, tmpl, tmph);
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tcg_gen_mulu2_tl(tmpl, tmph, ah, bl);
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tcg_gen_add2_tl(r1, tmph, r1, r2, tmpl, tmph);
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/* Overflow detection into r3 */
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tcg_gen_setcond_tl(TCG_COND_LTU, r3, tmph, r2);
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tcg_gen_mov_tl(r2, tmph);
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tcg_gen_mulu2_tl(tmpl, tmph, ah, bh);
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tcg_gen_add2_tl(r2, r3, r2, r3, tmpl, tmph);
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tcg_temp_free(tmpl);
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tcg_temp_free(tmph);
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}
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static void gen_mul_i128(TCGv rl, TCGv rh,
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TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
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{
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TCGv tmpl = tcg_temp_new();
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TCGv tmph = tcg_temp_new();
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TCGv tmpx = tcg_temp_new();
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TCGv zero = tcg_constant_tl(0);
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tcg_gen_mulu2_tl(rl, rh, rs1l, rs2l);
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tcg_gen_mulu2_tl(tmpl, tmph, rs1l, rs2h);
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tcg_gen_add2_tl(rh, tmpx, rh, zero, tmpl, tmph);
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tcg_gen_mulu2_tl(tmpl, tmph, rs1h, rs2l);
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tcg_gen_add2_tl(rh, tmph, rh, tmpx, tmpl, tmph);
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tcg_temp_free(tmpl);
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tcg_temp_free(tmph);
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tcg_temp_free(tmpx);
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}
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static bool trans_mul(DisasContext *ctx, arg_mul *a)
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{
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REQUIRE_EXT(ctx, RVM);
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return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl, gen_mul_i128);
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}
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static void gen_mulh_i128(TCGv rl, TCGv rh,
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TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
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{
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TCGv t0l = tcg_temp_new();
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TCGv t0h = tcg_temp_new();
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TCGv t1l = tcg_temp_new();
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TCGv t1h = tcg_temp_new();
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gen_mulhu_i128(rl, rh, rs1l, rs1h, rs2l, rs2h);
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tcg_gen_sari_tl(t0h, rs1h, 63);
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tcg_gen_and_tl(t0l, t0h, rs2l);
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tcg_gen_and_tl(t0h, t0h, rs2h);
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tcg_gen_sari_tl(t1h, rs2h, 63);
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tcg_gen_and_tl(t1l, t1h, rs1l);
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tcg_gen_and_tl(t1h, t1h, rs1h);
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tcg_gen_sub2_tl(t0l, t0h, rl, rh, t0l, t0h);
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tcg_gen_sub2_tl(rl, rh, t0l, t0h, t1l, t1h);
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tcg_temp_free(t0l);
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tcg_temp_free(t0h);
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tcg_temp_free(t1l);
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tcg_temp_free(t1h);
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}
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static void gen_mulh(TCGv ret, TCGv s1, TCGv s2)
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{
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TCGv discard = tcg_temp_new();
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tcg_gen_muls2_tl(discard, ret, s1, s2);
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tcg_temp_free(discard);
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}
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static void gen_mulh_w(TCGv ret, TCGv s1, TCGv s2)
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{
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tcg_gen_mul_tl(ret, s1, s2);
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tcg_gen_sari_tl(ret, ret, 32);
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}
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static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
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{
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REQUIRE_EXT(ctx, RVM);
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return gen_arith_per_ol(ctx, a, EXT_SIGN, gen_mulh, gen_mulh_w,
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gen_mulh_i128);
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}
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static void gen_mulhsu_i128(TCGv rl, TCGv rh,
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TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
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{
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TCGv t0l = tcg_temp_new();
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TCGv t0h = tcg_temp_new();
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gen_mulhu_i128(rl, rh, rs1l, rs1h, rs2l, rs2h);
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tcg_gen_sari_tl(t0h, rs1h, 63);
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tcg_gen_and_tl(t0l, t0h, rs2l);
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tcg_gen_and_tl(t0h, t0h, rs2h);
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tcg_gen_sub2_tl(rl, rh, rl, rh, t0l, t0h);
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tcg_temp_free(t0l);
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tcg_temp_free(t0h);
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}
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static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
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{
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TCGv rl = tcg_temp_new();
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TCGv rh = tcg_temp_new();
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tcg_gen_mulu2_tl(rl, rh, arg1, arg2);
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/* fix up for one negative */
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tcg_gen_sari_tl(rl, arg1, TARGET_LONG_BITS - 1);
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tcg_gen_and_tl(rl, rl, arg2);
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tcg_gen_sub_tl(ret, rh, rl);
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tcg_temp_free(rl);
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tcg_temp_free(rh);
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}
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static void gen_mulhsu_w(TCGv ret, TCGv arg1, TCGv arg2)
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{
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TCGv t1 = tcg_temp_new();
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TCGv t2 = tcg_temp_new();
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tcg_gen_ext32s_tl(t1, arg1);
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tcg_gen_ext32u_tl(t2, arg2);
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tcg_gen_mul_tl(ret, t1, t2);
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tcg_temp_free(t1);
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tcg_temp_free(t2);
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tcg_gen_sari_tl(ret, ret, 32);
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}
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static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
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{
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REQUIRE_EXT(ctx, RVM);
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return gen_arith_per_ol(ctx, a, EXT_NONE, gen_mulhsu, gen_mulhsu_w,
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gen_mulhsu_i128);
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}
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static void gen_mulhu(TCGv ret, TCGv s1, TCGv s2)
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{
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TCGv discard = tcg_temp_new();
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tcg_gen_mulu2_tl(discard, ret, s1, s2);
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tcg_temp_free(discard);
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}
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static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
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{
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REQUIRE_EXT(ctx, RVM);
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/* gen_mulh_w works for either sign as input. */
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return gen_arith_per_ol(ctx, a, EXT_ZERO, gen_mulhu, gen_mulh_w,
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gen_mulhu_i128);
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}
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static void gen_div_i128(TCGv rdl, TCGv rdh,
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TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
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{
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gen_helper_divs_i128(rdl, cpu_env, rs1l, rs1h, rs2l, rs2h);
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tcg_gen_ld_tl(rdh, cpu_env, offsetof(CPURISCVState, retxh));
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}
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static void gen_div(TCGv ret, TCGv source1, TCGv source2)
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{
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TCGv temp1, temp2, zero, one, mone, min;
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temp1 = tcg_temp_new();
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temp2 = tcg_temp_new();
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zero = tcg_constant_tl(0);
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one = tcg_constant_tl(1);
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mone = tcg_constant_tl(-1);
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min = tcg_constant_tl(1ull << (TARGET_LONG_BITS - 1));
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/*
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* If overflow, set temp2 to 1, else source2.
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* This produces the required result of min.
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*/
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tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min);
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tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone);
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tcg_gen_and_tl(temp1, temp1, temp2);
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tcg_gen_movcond_tl(TCG_COND_NE, temp2, temp1, zero, one, source2);
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/*
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* If div by zero, set temp1 to -1 and temp2 to 1 to
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* produce the required result of -1.
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*/
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tcg_gen_movcond_tl(TCG_COND_EQ, temp1, source2, zero, mone, source1);
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tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, temp2);
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tcg_gen_div_tl(ret, temp1, temp2);
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tcg_temp_free(temp1);
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tcg_temp_free(temp2);
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}
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static bool trans_div(DisasContext *ctx, arg_div *a)
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{
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REQUIRE_EXT(ctx, RVM);
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return gen_arith(ctx, a, EXT_SIGN, gen_div, gen_div_i128);
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}
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static void gen_divu_i128(TCGv rdl, TCGv rdh,
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TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
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{
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gen_helper_divu_i128(rdl, cpu_env, rs1l, rs1h, rs2l, rs2h);
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tcg_gen_ld_tl(rdh, cpu_env, offsetof(CPURISCVState, retxh));
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}
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static void gen_divu(TCGv ret, TCGv source1, TCGv source2)
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{
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TCGv temp1, temp2, zero, one, max;
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temp1 = tcg_temp_new();
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temp2 = tcg_temp_new();
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zero = tcg_constant_tl(0);
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one = tcg_constant_tl(1);
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max = tcg_constant_tl(~0);
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/*
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* If div by zero, set temp1 to max and temp2 to 1 to
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* produce the required result of max.
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*/
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tcg_gen_movcond_tl(TCG_COND_EQ, temp1, source2, zero, max, source1);
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tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, source2);
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tcg_gen_divu_tl(ret, temp1, temp2);
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tcg_temp_free(temp1);
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tcg_temp_free(temp2);
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}
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static bool trans_divu(DisasContext *ctx, arg_divu *a)
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{
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REQUIRE_EXT(ctx, RVM);
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return gen_arith(ctx, a, EXT_ZERO, gen_divu, gen_divu_i128);
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}
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static void gen_rem_i128(TCGv rdl, TCGv rdh,
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TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
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{
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gen_helper_rems_i128(rdl, cpu_env, rs1l, rs1h, rs2l, rs2h);
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tcg_gen_ld_tl(rdh, cpu_env, offsetof(CPURISCVState, retxh));
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}
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static void gen_rem(TCGv ret, TCGv source1, TCGv source2)
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{
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TCGv temp1, temp2, zero, one, mone, min;
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temp1 = tcg_temp_new();
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temp2 = tcg_temp_new();
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zero = tcg_constant_tl(0);
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one = tcg_constant_tl(1);
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mone = tcg_constant_tl(-1);
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min = tcg_constant_tl(1ull << (TARGET_LONG_BITS - 1));
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/*
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* If overflow, set temp1 to 0, else source1.
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* This avoids a possible host trap, and produces the required result of 0.
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*/
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tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min);
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tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone);
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tcg_gen_and_tl(temp1, temp1, temp2);
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tcg_gen_movcond_tl(TCG_COND_NE, temp1, temp1, zero, zero, source1);
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/*
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* If div by zero, set temp2 to 1, else source2.
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* This avoids a possible host trap, but produces an incorrect result.
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*/
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tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, source2);
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tcg_gen_rem_tl(temp1, temp1, temp2);
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/* If div by zero, the required result is the original dividend. */
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tcg_gen_movcond_tl(TCG_COND_EQ, ret, source2, zero, source1, temp1);
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tcg_temp_free(temp1);
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tcg_temp_free(temp2);
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}
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static bool trans_rem(DisasContext *ctx, arg_rem *a)
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{
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REQUIRE_EXT(ctx, RVM);
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return gen_arith(ctx, a, EXT_SIGN, gen_rem, gen_rem_i128);
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}
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static void gen_remu_i128(TCGv rdl, TCGv rdh,
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TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
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{
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gen_helper_remu_i128(rdl, cpu_env, rs1l, rs1h, rs2l, rs2h);
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tcg_gen_ld_tl(rdh, cpu_env, offsetof(CPURISCVState, retxh));
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}
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static void gen_remu(TCGv ret, TCGv source1, TCGv source2)
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{
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TCGv temp, zero, one;
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temp = tcg_temp_new();
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zero = tcg_constant_tl(0);
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one = tcg_constant_tl(1);
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/*
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* If div by zero, set temp to 1, else source2.
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* This avoids a possible host trap, but produces an incorrect result.
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*/
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tcg_gen_movcond_tl(TCG_COND_EQ, temp, source2, zero, one, source2);
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tcg_gen_remu_tl(temp, source1, temp);
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/* If div by zero, the required result is the original dividend. */
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tcg_gen_movcond_tl(TCG_COND_EQ, ret, source2, zero, source1, temp);
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tcg_temp_free(temp);
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}
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static bool trans_remu(DisasContext *ctx, arg_remu *a)
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{
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REQUIRE_EXT(ctx, RVM);
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return gen_arith(ctx, a, EXT_ZERO, gen_remu, gen_remu_i128);
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}
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static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
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{
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REQUIRE_64_OR_128BIT(ctx);
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REQUIRE_EXT(ctx, RVM);
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ctx->ol = MXL_RV32;
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return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl, NULL);
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}
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static bool trans_divw(DisasContext *ctx, arg_divw *a)
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{
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REQUIRE_64_OR_128BIT(ctx);
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REQUIRE_EXT(ctx, RVM);
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ctx->ol = MXL_RV32;
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return gen_arith(ctx, a, EXT_SIGN, gen_div, NULL);
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}
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static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
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{
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REQUIRE_64_OR_128BIT(ctx);
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REQUIRE_EXT(ctx, RVM);
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ctx->ol = MXL_RV32;
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return gen_arith(ctx, a, EXT_ZERO, gen_divu, NULL);
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}
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static bool trans_remw(DisasContext *ctx, arg_remw *a)
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{
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REQUIRE_64_OR_128BIT(ctx);
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REQUIRE_EXT(ctx, RVM);
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ctx->ol = MXL_RV32;
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return gen_arith(ctx, a, EXT_SIGN, gen_rem, NULL);
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}
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static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
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{
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REQUIRE_64_OR_128BIT(ctx);
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REQUIRE_EXT(ctx, RVM);
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ctx->ol = MXL_RV32;
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return gen_arith(ctx, a, EXT_ZERO, gen_remu, NULL);
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}
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static bool trans_muld(DisasContext *ctx, arg_muld *a)
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{
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REQUIRE_128BIT(ctx);
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REQUIRE_EXT(ctx, RVM);
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ctx->ol = MXL_RV64;
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return gen_arith(ctx, a, EXT_SIGN, tcg_gen_mul_tl, NULL);
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}
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static bool trans_divd(DisasContext *ctx, arg_divd *a)
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{
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REQUIRE_128BIT(ctx);
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REQUIRE_EXT(ctx, RVM);
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ctx->ol = MXL_RV64;
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return gen_arith(ctx, a, EXT_SIGN, gen_div, NULL);
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}
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static bool trans_divud(DisasContext *ctx, arg_divud *a)
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{
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REQUIRE_128BIT(ctx);
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REQUIRE_EXT(ctx, RVM);
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ctx->ol = MXL_RV64;
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return gen_arith(ctx, a, EXT_ZERO, gen_divu, NULL);
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}
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static bool trans_remd(DisasContext *ctx, arg_remd *a)
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{
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REQUIRE_128BIT(ctx);
|
|
REQUIRE_EXT(ctx, RVM);
|
|
ctx->ol = MXL_RV64;
|
|
return gen_arith(ctx, a, EXT_SIGN, gen_rem, NULL);
|
|
}
|
|
|
|
static bool trans_remud(DisasContext *ctx, arg_remud *a)
|
|
{
|
|
REQUIRE_128BIT(ctx);
|
|
REQUIRE_EXT(ctx, RVM);
|
|
ctx->ol = MXL_RV64;
|
|
return gen_arith(ctx, a, EXT_ZERO, gen_remu, NULL);
|
|
}
|