b3a5d1fbeb
Mult are generated inline (using a cool trick pointed out by Richard), but for div and rem, given the complexity of the implementation of these instructions, we call helpers to produce their behavior. From an implementation standpoint, the helpers return the low part of the results, while the high part is temporarily stored in a dedicated field of cpu_env that is used to update the architectural register in the generation wrapper. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-15-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
34 lines
722 B
Meson
34 lines
722 B
Meson
# FIXME extra_args should accept files()
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dir = meson.current_source_dir()
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gen = [
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decodetree.process('insn16.decode', extra_args: ['--static-decode=decode_insn16', '--insnwidth=16']),
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decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'),
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]
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riscv_ss = ss.source_set()
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riscv_ss.add(gen)
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riscv_ss.add(files(
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'cpu.c',
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'cpu_helper.c',
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'csr.c',
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'fpu_helper.c',
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'gdbstub.c',
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'op_helper.c',
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'vector_helper.c',
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'bitmanip_helper.c',
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'translate.c',
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'm128_helper.c'
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))
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riscv_softmmu_ss = ss.source_set()
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riscv_softmmu_ss.add(files(
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'arch_dump.c',
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'pmp.c',
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'monitor.c',
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'machine.c'
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))
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target_arch += {'riscv': riscv_ss}
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target_softmmu_arch += {'riscv': riscv_softmmu_ss}
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