d3bad7e7c4
The number of MACs supported by an Aspeed SoC is defined by "macs_num"
under the SoC model, that is two for the AST2400 and AST2500 and four
for the AST2600. The model initializes the maximum number of supported
MACs but the number of realized devices is capped by the number of
network device back-ends defined on the command line. This can leave
unrealized devices hanging around in the QOM composition tree.
To get virtual hardware that matches the physical hardware, you have
to pass exactly as many -nic options as there are MACs, and some of
them must be -nic none:
* Machines ast2500-evb, palmetto-bmc, romulus-bmc, sonorapass-bmc,
swift-bmc, and witherspoon-bmc: two -nic, and the second one must be
-nic none.
* Machine ast2600-evb: four -nic, the first one must be -nic none.
* Machine tacoma-bmc: four nic, the first two and the last one must be
-nic none.
Modify the machine initialization to define which MACs are attached to
a network device back-end using a bit-field property "macs-mask" and
let the SoC realize all network devices.
The default setting of "macs-mask" is "use MAC0" only, which works for
all our AST2400 and AST2500 machines. The AST2600 machines have
different configurations. The AST2600 EVB machine activates MAC1, MAC2
and MAC3 and the Tacoma BMC machine activates MAC2.
Incompatible CLI change: -nic options now apply to *active* MACs:
MAC1, MAC2, MAC3 for ast2600-evb, MAC2 for tacoma-bmc, and MAC0 for
all the others.
The machines now always get all MACs as they should. Visible in "info
qom-tree", here's the change for tacoma-bmc:
/machine (tacoma-bmc-machine)
/peripheral (container)
/peripheral-anon (container)
/soc (ast2600-a1)
[...]
/ftgmac100[0] (ftgmac100)
/ftgmac100[0] (qemu:memory-region)
/ftgmac100[1] (ftgmac100)
+ /ftgmac100[0] (qemu:memory-region)
/ftgmac100[2] (ftgmac100)
+ /ftgmac100[0] (qemu:memory-region)
/ftgmac100[3] (ftgmac100)
+ /ftgmac100[0] (qemu:memory-region)
[...]
/mii[0] (aspeed-mmi)
/aspeed-mmi[0] (qemu:memory-region)
/mii[1] (aspeed-mmi)
+ /aspeed-mmi[0] (qemu:memory-region)
/mii[2] (aspeed-mmi)
+ /aspeed-mmi[0] (qemu:memory-region)
/mii[3] (aspeed-mmi)
+ /aspeed-mmi[0] (qemu:memory-region)
Also visible in "info qtree"; here's the change for tacoma-bmc:
dev: ftgmac100, id ""
gpio-out "sysbus-irq" 1
aspeed = true
- mac = "52:54:00:12:34:56"
- netdev = "hub0port0"
+ mac = "52:54:00:12:34:57"
+ netdev = ""
mmio 000000001e660000/0000000000002000
dev: ftgmac100, id ""
- aspeed = false
- mac = "00:00:00:00:00:00"
+ gpio-out "sysbus-irq" 1
+ aspeed = true
+ mac = "52:54:00:12:34:58"
netdev = ""
+ mmio 000000001e680000/0000000000002000
dev: ftgmac100, id ""
- aspeed = false
- mac = "00:00:00:00:00:00"
- netdev = ""
+ gpio-out "sysbus-irq" 1
+ aspeed = true
+ mac = "52:54:00:12:34:56"
+ netdev = "hub0port0"
+ mmio 000000001e670000/0000000000002000
dev: ftgmac100, id ""
- aspeed = false
- mac = "00:00:00:00:00:00"
+ gpio-out "sysbus-irq" 1
+ aspeed = true
+ mac = "52:54:00:12:34:59"
netdev = ""
+ mmio 000000001e690000/0000000000002000
[...]
dev: aspeed-mmi, id ""
mmio 000000001e650000/0000000000000008
dev: aspeed-mmi, id ""
+ mmio 000000001e650008/0000000000000008
dev: aspeed-mmi, id ""
+ mmio 000000001e650010/0000000000000008
dev: aspeed-mmi, id ""
+ mmio 000000001e650018/0000000000000008
Inactive MACs will have no peer and QEMU may warn the user with :
qemu-system-arm: warning: nic ftgmac100.0 has no peer
qemu-system-arm: warning: nic ftgmac100.1 has no peer
qemu-system-arm: warning: nic ftgmac100.3 has no peer
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
[Commit message expanded]
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20200609122339.937862-6-armbru@redhat.com>
580 lines
20 KiB
C
580 lines
20 KiB
C
/*
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* ASPEED SoC 2600 family
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*
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* Copyright (c) 2016-2019, IBM Corporation.
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "exec/address-spaces.h"
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#include "hw/misc/unimp.h"
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#include "hw/arm/aspeed_soc.h"
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#include "hw/char/serial.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "qemu/error-report.h"
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#include "hw/i2c/aspeed_i2c.h"
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#include "net/net.h"
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#include "sysemu/sysemu.h"
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#define ASPEED_SOC_IOMEM_SIZE 0x00200000
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static const hwaddr aspeed_soc_ast2600_memmap[] = {
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[ASPEED_SRAM] = 0x10000000,
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/* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */
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[ASPEED_IOMEM] = 0x1E600000,
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[ASPEED_PWM] = 0x1E610000,
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[ASPEED_FMC] = 0x1E620000,
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[ASPEED_SPI1] = 0x1E630000,
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[ASPEED_SPI2] = 0x1E641000,
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[ASPEED_EHCI1] = 0x1E6A1000,
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[ASPEED_EHCI2] = 0x1E6A3000,
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[ASPEED_MII1] = 0x1E650000,
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[ASPEED_MII2] = 0x1E650008,
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[ASPEED_MII3] = 0x1E650010,
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[ASPEED_MII4] = 0x1E650018,
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[ASPEED_ETH1] = 0x1E660000,
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[ASPEED_ETH3] = 0x1E670000,
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[ASPEED_ETH2] = 0x1E680000,
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[ASPEED_ETH4] = 0x1E690000,
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[ASPEED_VIC] = 0x1E6C0000,
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[ASPEED_SDMC] = 0x1E6E0000,
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[ASPEED_SCU] = 0x1E6E2000,
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[ASPEED_XDMA] = 0x1E6E7000,
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[ASPEED_ADC] = 0x1E6E9000,
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[ASPEED_VIDEO] = 0x1E700000,
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[ASPEED_SDHCI] = 0x1E740000,
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[ASPEED_EMMC] = 0x1E750000,
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[ASPEED_GPIO] = 0x1E780000,
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[ASPEED_GPIO_1_8V] = 0x1E780800,
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[ASPEED_RTC] = 0x1E781000,
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[ASPEED_TIMER1] = 0x1E782000,
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[ASPEED_WDT] = 0x1E785000,
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[ASPEED_LPC] = 0x1E789000,
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[ASPEED_IBT] = 0x1E789140,
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[ASPEED_I2C] = 0x1E78A000,
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[ASPEED_UART1] = 0x1E783000,
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[ASPEED_UART5] = 0x1E784000,
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[ASPEED_VUART] = 0x1E787000,
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[ASPEED_SDRAM] = 0x80000000,
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};
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#define ASPEED_A7MPCORE_ADDR 0x40460000
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#define ASPEED_SOC_AST2600_MAX_IRQ 128
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/* Shared Peripheral Interrupt values below are offset by -32 from datasheet */
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static const int aspeed_soc_ast2600_irqmap[] = {
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[ASPEED_UART1] = 47,
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[ASPEED_UART2] = 48,
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[ASPEED_UART3] = 49,
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[ASPEED_UART4] = 50,
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[ASPEED_UART5] = 8,
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[ASPEED_VUART] = 8,
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[ASPEED_FMC] = 39,
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[ASPEED_SDMC] = 0,
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[ASPEED_SCU] = 12,
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[ASPEED_ADC] = 78,
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[ASPEED_XDMA] = 6,
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[ASPEED_SDHCI] = 43,
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[ASPEED_EHCI1] = 5,
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[ASPEED_EHCI2] = 9,
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[ASPEED_EMMC] = 15,
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[ASPEED_GPIO] = 40,
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[ASPEED_GPIO_1_8V] = 11,
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[ASPEED_RTC] = 13,
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[ASPEED_TIMER1] = 16,
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[ASPEED_TIMER2] = 17,
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[ASPEED_TIMER3] = 18,
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[ASPEED_TIMER4] = 19,
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[ASPEED_TIMER5] = 20,
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[ASPEED_TIMER6] = 21,
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[ASPEED_TIMER7] = 22,
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[ASPEED_TIMER8] = 23,
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[ASPEED_WDT] = 24,
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[ASPEED_PWM] = 44,
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[ASPEED_LPC] = 35,
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[ASPEED_IBT] = 35, /* LPC */
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[ASPEED_I2C] = 110, /* 110 -> 125 */
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[ASPEED_ETH1] = 2,
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[ASPEED_ETH2] = 3,
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[ASPEED_ETH3] = 32,
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[ASPEED_ETH4] = 33,
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};
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static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
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{
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AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
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return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[ctrl]);
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}
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static void aspeed_soc_ast2600_init(Object *obj)
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{
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AspeedSoCState *s = ASPEED_SOC(obj);
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AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
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int i;
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char socname[8];
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char typename[64];
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if (sscanf(sc->name, "%7s", socname) != 1) {
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g_assert_not_reached();
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}
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for (i = 0; i < sc->num_cpus; i++) {
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object_initialize_child(obj, "cpu[*]", OBJECT(&s->cpu[i]),
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sizeof(s->cpu[i]), sc->cpu_type,
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&error_abort, NULL);
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}
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snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
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sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu),
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typename);
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qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
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sc->silicon_rev);
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object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
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"hw-strap1");
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object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
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"hw-strap2");
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object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
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"hw-prot-key");
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sysbus_init_child_obj(obj, "a7mpcore", &s->a7mpcore,
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sizeof(s->a7mpcore), TYPE_A15MPCORE_PRIV);
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sysbus_init_child_obj(obj, "rtc", OBJECT(&s->rtc), sizeof(s->rtc),
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TYPE_ASPEED_RTC);
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snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
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sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl),
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sizeof(s->timerctrl), typename);
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snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
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sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c),
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typename);
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snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
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sysbus_init_child_obj(obj, "fmc", OBJECT(&s->fmc), sizeof(s->fmc),
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typename);
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object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs");
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for (i = 0; i < sc->spis_num; i++) {
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snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
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sysbus_init_child_obj(obj, "spi[*]", OBJECT(&s->spi[i]),
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sizeof(s->spi[i]), typename);
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}
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for (i = 0; i < sc->ehcis_num; i++) {
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sysbus_init_child_obj(obj, "ehci[*]", OBJECT(&s->ehci[i]),
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sizeof(s->ehci[i]), TYPE_PLATFORM_EHCI);
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}
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snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
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sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc),
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typename);
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object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
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"ram-size");
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object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc),
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"max-ram-size");
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for (i = 0; i < sc->wdts_num; i++) {
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snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
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sysbus_init_child_obj(obj, "wdt[*]", OBJECT(&s->wdt[i]),
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sizeof(s->wdt[i]), typename);
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}
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for (i = 0; i < sc->macs_num; i++) {
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sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]),
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sizeof(s->ftgmac100[i]), TYPE_FTGMAC100);
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sysbus_init_child_obj(obj, "mii[*]", &s->mii[i], sizeof(s->mii[i]),
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TYPE_ASPEED_MII);
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}
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sysbus_init_child_obj(obj, "xdma", OBJECT(&s->xdma), sizeof(s->xdma),
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TYPE_ASPEED_XDMA);
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snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
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sysbus_init_child_obj(obj, "gpio", OBJECT(&s->gpio), sizeof(s->gpio),
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typename);
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snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname);
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sysbus_init_child_obj(obj, "gpio_1_8v", OBJECT(&s->gpio_1_8v),
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sizeof(s->gpio_1_8v), typename);
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sysbus_init_child_obj(obj, "sd-controller", OBJECT(&s->sdhci),
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sizeof(s->sdhci), TYPE_ASPEED_SDHCI);
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object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort);
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/* Init sd card slot class here so that they're under the correct parent */
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for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
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sysbus_init_child_obj(obj, "sd-controller.sdhci[*]",
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OBJECT(&s->sdhci.slots[i]),
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sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI);
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}
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sysbus_init_child_obj(obj, "emmc-controller", OBJECT(&s->emmc),
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sizeof(s->emmc), TYPE_ASPEED_SDHCI);
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object_property_set_int(OBJECT(&s->emmc), 1, "num-slots", &error_abort);
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sysbus_init_child_obj(obj, "emmc-controller.sdhci",
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OBJECT(&s->emmc.slots[0]), sizeof(s->emmc.slots[0]),
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TYPE_SYSBUS_SDHCI);
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}
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/*
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* ASPEED ast2600 has 0xf as cluster ID
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*
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* http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388e/CIHEBGFG.html
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*/
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static uint64_t aspeed_calc_affinity(int cpu)
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{
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return (0xf << ARM_AFF1_SHIFT) | cpu;
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}
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static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
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{
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int i;
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AspeedSoCState *s = ASPEED_SOC(dev);
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AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
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Error *err = NULL, *local_err = NULL;
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qemu_irq irq;
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/* IO space */
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create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_IOMEM],
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ASPEED_SOC_IOMEM_SIZE);
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/* Video engine stub */
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create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_VIDEO],
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0x1000);
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/* CPU */
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for (i = 0; i < sc->num_cpus; i++) {
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object_property_set_int(OBJECT(&s->cpu[i]), QEMU_PSCI_CONDUIT_SMC,
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"psci-conduit", &error_abort);
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if (sc->num_cpus > 1) {
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object_property_set_int(OBJECT(&s->cpu[i]),
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ASPEED_A7MPCORE_ADDR,
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"reset-cbar", &error_abort);
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}
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object_property_set_int(OBJECT(&s->cpu[i]), aspeed_calc_affinity(i),
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"mp-affinity", &error_abort);
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object_property_set_int(OBJECT(&s->cpu[i]), 1125000000, "cntfrq",
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&error_abort);
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/*
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* TODO: the secondary CPUs are started and a boot helper
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* is needed when using -kernel
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*/
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object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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}
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/* A7MPCORE */
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object_property_set_int(OBJECT(&s->a7mpcore), sc->num_cpus, "num-cpu",
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&error_abort);
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object_property_set_int(OBJECT(&s->a7mpcore),
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ASPEED_SOC_AST2600_MAX_IRQ + GIC_INTERNAL,
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"num-irq", &error_abort);
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object_property_set_bool(OBJECT(&s->a7mpcore), true, "realized",
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&error_abort);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR);
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for (i = 0; i < sc->num_cpus; i++) {
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SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
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DeviceState *d = DEVICE(qemu_get_cpu(i));
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irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
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sysbus_connect_irq(sbd, i, irq);
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irq = qdev_get_gpio_in(d, ARM_CPU_FIQ);
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sysbus_connect_irq(sbd, i + sc->num_cpus, irq);
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irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ);
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sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq);
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irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ);
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sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq);
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}
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/* SRAM */
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memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
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sc->sram_size, &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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memory_region_add_subregion(get_system_memory(),
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sc->memmap[ASPEED_SRAM], &s->sram);
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/* SCU */
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object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_SCU]);
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/* RTC */
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object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_RTC]);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
|
|
aspeed_soc_get_irq(s, ASPEED_RTC));
|
|
|
|
/* Timer */
|
|
object_property_set_link(OBJECT(&s->timerctrl),
|
|
OBJECT(&s->scu), "scu", &error_abort);
|
|
object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
|
|
if (err) {
|
|
error_propagate(errp, err);
|
|
return;
|
|
}
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0,
|
|
sc->memmap[ASPEED_TIMER1]);
|
|
for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
|
|
qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
|
|
}
|
|
|
|
/* UART - attach an 8250 to the IO space as our UART5 */
|
|
if (serial_hd(0)) {
|
|
qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5);
|
|
serial_mm_init(get_system_memory(), sc->memmap[ASPEED_UART5], 2,
|
|
uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
|
|
}
|
|
|
|
/* I2C */
|
|
object_property_set_link(OBJECT(&s->i2c), OBJECT(s->dram_mr), "dram", &err);
|
|
if (err) {
|
|
error_propagate(errp, err);
|
|
return;
|
|
}
|
|
object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err);
|
|
if (err) {
|
|
error_propagate(errp, err);
|
|
return;
|
|
}
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_I2C]);
|
|
for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
|
|
qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
|
|
sc->irqmap[ASPEED_I2C] + i);
|
|
/*
|
|
* The AST2600 SoC has one IRQ per I2C bus. Skip the common
|
|
* IRQ (AST2400 and AST2500) and connect all bussses.
|
|
*/
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), i + 1, irq);
|
|
}
|
|
|
|
/* FMC, The number of CS is set at the board level */
|
|
object_property_set_link(OBJECT(&s->fmc), OBJECT(s->dram_mr), "dram", &err);
|
|
if (err) {
|
|
error_propagate(errp, err);
|
|
return;
|
|
}
|
|
object_property_set_int(OBJECT(&s->fmc), sc->memmap[ASPEED_SDRAM],
|
|
"sdram-base", &err);
|
|
if (err) {
|
|
error_propagate(errp, err);
|
|
return;
|
|
}
|
|
object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err);
|
|
if (err) {
|
|
error_propagate(errp, err);
|
|
return;
|
|
}
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_FMC]);
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
|
|
s->fmc.ctrl->flash_window_base);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
|
|
aspeed_soc_get_irq(s, ASPEED_FMC));
|
|
|
|
/* SPI */
|
|
for (i = 0; i < sc->spis_num; i++) {
|
|
object_property_set_link(OBJECT(&s->spi[i]), OBJECT(s->dram_mr),
|
|
"dram", &err);
|
|
if (err) {
|
|
error_propagate(errp, err);
|
|
return;
|
|
}
|
|
object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err);
|
|
object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
|
|
&local_err);
|
|
error_propagate(&err, local_err);
|
|
if (err) {
|
|
error_propagate(errp, err);
|
|
return;
|
|
}
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
|
|
sc->memmap[ASPEED_SPI1 + i]);
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
|
|
s->spi[i].ctrl->flash_window_base);
|
|
}
|
|
|
|
/* EHCI */
|
|
for (i = 0; i < sc->ehcis_num; i++) {
|
|
object_property_set_bool(OBJECT(&s->ehci[i]), true, "realized", &err);
|
|
if (err) {
|
|
error_propagate(errp, err);
|
|
return;
|
|
}
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0,
|
|
sc->memmap[ASPEED_EHCI1 + i]);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
|
|
aspeed_soc_get_irq(s, ASPEED_EHCI1 + i));
|
|
}
|
|
|
|
/* SDMC - SDRAM Memory Controller */
|
|
object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
|
|
if (err) {
|
|
error_propagate(errp, err);
|
|
return;
|
|
}
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_SDMC]);
|
|
|
|
/* Watch dog */
|
|
for (i = 0; i < sc->wdts_num; i++) {
|
|
AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
|
|
|
|
object_property_set_link(OBJECT(&s->wdt[i]),
|
|
OBJECT(&s->scu), "scu", &error_abort);
|
|
object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err);
|
|
if (err) {
|
|
error_propagate(errp, err);
|
|
return;
|
|
}
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
|
|
sc->memmap[ASPEED_WDT] + i * awc->offset);
|
|
}
|
|
|
|
/* Net */
|
|
for (i = 0; i < sc->macs_num; i++) {
|
|
object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed",
|
|
&err);
|
|
object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "realized",
|
|
&local_err);
|
|
error_propagate(&err, local_err);
|
|
if (err) {
|
|
error_propagate(errp, err);
|
|
return;
|
|
}
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
|
|
sc->memmap[ASPEED_ETH1 + i]);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
|
|
aspeed_soc_get_irq(s, ASPEED_ETH1 + i));
|
|
|
|
object_property_set_link(OBJECT(&s->mii[i]), OBJECT(&s->ftgmac100[i]),
|
|
"nic", &error_abort);
|
|
object_property_set_bool(OBJECT(&s->mii[i]), true, "realized",
|
|
&err);
|
|
if (err) {
|
|
error_propagate(errp, err);
|
|
return;
|
|
}
|
|
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->mii[i]), 0,
|
|
sc->memmap[ASPEED_MII1 + i]);
|
|
}
|
|
|
|
/* XDMA */
|
|
object_property_set_bool(OBJECT(&s->xdma), true, "realized", &err);
|
|
if (err) {
|
|
error_propagate(errp, err);
|
|
return;
|
|
}
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0,
|
|
sc->memmap[ASPEED_XDMA]);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
|
|
aspeed_soc_get_irq(s, ASPEED_XDMA));
|
|
|
|
/* GPIO */
|
|
object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
|
|
if (err) {
|
|
error_propagate(errp, err);
|
|
return;
|
|
}
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_GPIO]);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
|
|
aspeed_soc_get_irq(s, ASPEED_GPIO));
|
|
|
|
object_property_set_bool(OBJECT(&s->gpio_1_8v), true, "realized", &err);
|
|
if (err) {
|
|
error_propagate(errp, err);
|
|
return;
|
|
}
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio_1_8v), 0,
|
|
sc->memmap[ASPEED_GPIO_1_8V]);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0,
|
|
aspeed_soc_get_irq(s, ASPEED_GPIO_1_8V));
|
|
|
|
/* SDHCI */
|
|
object_property_set_bool(OBJECT(&s->sdhci), true, "realized", &err);
|
|
if (err) {
|
|
error_propagate(errp, err);
|
|
return;
|
|
}
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
|
|
sc->memmap[ASPEED_SDHCI]);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
|
|
aspeed_soc_get_irq(s, ASPEED_SDHCI));
|
|
|
|
/* eMMC */
|
|
object_property_set_bool(OBJECT(&s->emmc), true, "realized", &err);
|
|
if (err) {
|
|
error_propagate(errp, err);
|
|
return;
|
|
}
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_EMMC]);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0,
|
|
aspeed_soc_get_irq(s, ASPEED_EMMC));
|
|
}
|
|
|
|
static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
|
|
|
|
dc->realize = aspeed_soc_ast2600_realize;
|
|
|
|
sc->name = "ast2600-a1";
|
|
sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
|
|
sc->silicon_rev = AST2600_A1_SILICON_REV;
|
|
sc->sram_size = 0x10000;
|
|
sc->spis_num = 2;
|
|
sc->ehcis_num = 2;
|
|
sc->wdts_num = 4;
|
|
sc->macs_num = 4;
|
|
sc->irqmap = aspeed_soc_ast2600_irqmap;
|
|
sc->memmap = aspeed_soc_ast2600_memmap;
|
|
sc->num_cpus = 2;
|
|
}
|
|
|
|
static const TypeInfo aspeed_soc_ast2600_type_info = {
|
|
.name = "ast2600-a1",
|
|
.parent = TYPE_ASPEED_SOC,
|
|
.instance_size = sizeof(AspeedSoCState),
|
|
.instance_init = aspeed_soc_ast2600_init,
|
|
.class_init = aspeed_soc_ast2600_class_init,
|
|
.class_size = sizeof(AspeedSoCClass),
|
|
};
|
|
|
|
static void aspeed_soc_register_types(void)
|
|
{
|
|
type_register_static(&aspeed_soc_ast2600_type_info);
|
|
};
|
|
|
|
type_init(aspeed_soc_register_types)
|