Move the following instructions to decodetree: ddedpd: DFP Decode DPD To BCD ddedpdq: DFP Decode DPD To BCD Quad denbcd: DFP Encode BCD To DPD denbcdq: DFP Encode BCD To DPD Quad dscli: DFP Shift Significand Left Immediate dscliq: DFP Shift Significand Left Immediate Quad dscri: DFP Shift Significand Right Immediate dscriq: DFP Shift Significand Right Immediate Quad Also deleted dfp-ops.c.inc, now that all PPC DFP instructions were moved to decodetree. Signed-off-by: Luis Pires <luis.pires@eldorado.org.br> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211029192417.400707-16-luis.pires@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
230 lines
9.7 KiB
C++
230 lines
9.7 KiB
C++
/*** Decimal Floating Point ***/
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static inline TCGv_ptr gen_fprp_ptr(int reg)
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{
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TCGv_ptr r = tcg_temp_new_ptr();
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tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, vsr[reg].u64[0]));
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return r;
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}
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#define TRANS_DFP_T_A_B_Rc(NAME) \
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static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
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{ \
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TCGv_ptr rt, ra, rb; \
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REQUIRE_INSNS_FLAGS2(ctx, DFP); \
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REQUIRE_FPU(ctx); \
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rt = gen_fprp_ptr(a->rt); \
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ra = gen_fprp_ptr(a->ra); \
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rb = gen_fprp_ptr(a->rb); \
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gen_helper_##NAME(cpu_env, rt, ra, rb); \
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if (unlikely(a->rc)) { \
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gen_set_cr1_from_fpscr(ctx); \
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} \
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tcg_temp_free_ptr(rt); \
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tcg_temp_free_ptr(ra); \
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tcg_temp_free_ptr(rb); \
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return true; \
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}
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#define TRANS_DFP_BF_A_B(NAME) \
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static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
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{ \
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TCGv_ptr ra, rb; \
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REQUIRE_INSNS_FLAGS2(ctx, DFP); \
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REQUIRE_FPU(ctx); \
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ra = gen_fprp_ptr(a->ra); \
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rb = gen_fprp_ptr(a->rb); \
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gen_helper_##NAME(cpu_crf[a->bf], \
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cpu_env, ra, rb); \
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tcg_temp_free_ptr(ra); \
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tcg_temp_free_ptr(rb); \
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return true; \
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}
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#define TRANS_DFP_BF_I_B(NAME) \
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static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
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{ \
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TCGv_ptr rb; \
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REQUIRE_INSNS_FLAGS2(ctx, DFP); \
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REQUIRE_FPU(ctx); \
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rb = gen_fprp_ptr(a->rb); \
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gen_helper_##NAME(cpu_crf[a->bf], \
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cpu_env, tcg_constant_i32(a->uim), rb);\
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tcg_temp_free_ptr(rb); \
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return true; \
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}
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#define TRANS_DFP_BF_A_DCM(NAME) \
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static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
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{ \
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TCGv_ptr ra; \
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REQUIRE_INSNS_FLAGS2(ctx, DFP); \
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REQUIRE_FPU(ctx); \
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ra = gen_fprp_ptr(a->fra); \
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gen_helper_##NAME(cpu_crf[a->bf], \
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cpu_env, ra, tcg_constant_i32(a->dm)); \
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tcg_temp_free_ptr(ra); \
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return true; \
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}
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#define TRANS_DFP_T_B_U32_U32_Rc(NAME, U32F1, U32F2) \
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static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
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{ \
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TCGv_ptr rt, rb; \
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REQUIRE_INSNS_FLAGS2(ctx, DFP); \
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REQUIRE_FPU(ctx); \
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rt = gen_fprp_ptr(a->frt); \
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rb = gen_fprp_ptr(a->frb); \
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gen_helper_##NAME(cpu_env, rt, rb, \
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tcg_constant_i32(a->U32F1), \
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tcg_constant_i32(a->U32F2)); \
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if (unlikely(a->rc)) { \
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gen_set_cr1_from_fpscr(ctx); \
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} \
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tcg_temp_free_ptr(rt); \
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tcg_temp_free_ptr(rb); \
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return true; \
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}
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#define TRANS_DFP_T_A_B_I32_Rc(NAME, I32FLD) \
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static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
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{ \
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TCGv_ptr rt, ra, rb; \
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REQUIRE_INSNS_FLAGS2(ctx, DFP); \
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REQUIRE_FPU(ctx); \
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rt = gen_fprp_ptr(a->frt); \
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ra = gen_fprp_ptr(a->fra); \
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rb = gen_fprp_ptr(a->frb); \
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gen_helper_##NAME(cpu_env, rt, ra, rb, \
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tcg_constant_i32(a->I32FLD)); \
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if (unlikely(a->rc)) { \
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gen_set_cr1_from_fpscr(ctx); \
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} \
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tcg_temp_free_ptr(rt); \
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tcg_temp_free_ptr(ra); \
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tcg_temp_free_ptr(rb); \
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return true; \
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}
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#define TRANS_DFP_T_B_Rc(NAME) \
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static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
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{ \
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TCGv_ptr rt, rb; \
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REQUIRE_INSNS_FLAGS2(ctx, DFP); \
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REQUIRE_FPU(ctx); \
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rt = gen_fprp_ptr(a->rt); \
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rb = gen_fprp_ptr(a->rb); \
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gen_helper_##NAME(cpu_env, rt, rb); \
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if (unlikely(a->rc)) { \
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gen_set_cr1_from_fpscr(ctx); \
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} \
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tcg_temp_free_ptr(rt); \
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tcg_temp_free_ptr(rb); \
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return true; \
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}
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#define TRANS_DFP_T_FPR_I32_Rc(NAME, FPRFLD, I32FLD) \
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static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
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{ \
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TCGv_ptr rt, rx; \
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REQUIRE_INSNS_FLAGS2(ctx, DFP); \
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REQUIRE_FPU(ctx); \
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rt = gen_fprp_ptr(a->rt); \
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rx = gen_fprp_ptr(a->FPRFLD); \
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gen_helper_##NAME(cpu_env, rt, rx, \
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tcg_constant_i32(a->I32FLD)); \
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if (unlikely(a->rc)) { \
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gen_set_cr1_from_fpscr(ctx); \
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} \
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tcg_temp_free_ptr(rt); \
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tcg_temp_free_ptr(rx); \
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return true; \
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}
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TRANS_DFP_T_A_B_Rc(DADD)
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TRANS_DFP_T_A_B_Rc(DADDQ)
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TRANS_DFP_T_A_B_Rc(DSUB)
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TRANS_DFP_T_A_B_Rc(DSUBQ)
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TRANS_DFP_T_A_B_Rc(DMUL)
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TRANS_DFP_T_A_B_Rc(DMULQ)
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TRANS_DFP_T_A_B_Rc(DDIV)
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TRANS_DFP_T_A_B_Rc(DDIVQ)
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TRANS_DFP_BF_A_B(DCMPU)
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TRANS_DFP_BF_A_B(DCMPUQ)
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TRANS_DFP_BF_A_B(DCMPO)
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TRANS_DFP_BF_A_B(DCMPOQ)
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TRANS_DFP_BF_A_DCM(DTSTDC)
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TRANS_DFP_BF_A_DCM(DTSTDCQ)
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TRANS_DFP_BF_A_DCM(DTSTDG)
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TRANS_DFP_BF_A_DCM(DTSTDGQ)
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TRANS_DFP_BF_A_B(DTSTEX)
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TRANS_DFP_BF_A_B(DTSTEXQ)
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TRANS_DFP_BF_A_B(DTSTSF)
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TRANS_DFP_BF_A_B(DTSTSFQ)
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TRANS_DFP_BF_I_B(DTSTSFI)
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TRANS_DFP_BF_I_B(DTSTSFIQ)
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TRANS_DFP_T_B_U32_U32_Rc(DQUAI, te, rmc)
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TRANS_DFP_T_B_U32_U32_Rc(DQUAIQ, te, rmc)
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TRANS_DFP_T_A_B_I32_Rc(DQUA, rmc)
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TRANS_DFP_T_A_B_I32_Rc(DQUAQ, rmc)
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TRANS_DFP_T_A_B_I32_Rc(DRRND, rmc)
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TRANS_DFP_T_A_B_I32_Rc(DRRNDQ, rmc)
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TRANS_DFP_T_B_U32_U32_Rc(DRINTX, r, rmc)
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TRANS_DFP_T_B_U32_U32_Rc(DRINTXQ, r, rmc)
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TRANS_DFP_T_B_U32_U32_Rc(DRINTN, r, rmc)
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TRANS_DFP_T_B_U32_U32_Rc(DRINTNQ, r, rmc)
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TRANS_DFP_T_B_Rc(DCTDP)
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TRANS_DFP_T_B_Rc(DCTQPQ)
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TRANS_DFP_T_B_Rc(DRSP)
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TRANS_DFP_T_B_Rc(DRDPQ)
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TRANS_DFP_T_B_Rc(DCFFIX)
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TRANS_DFP_T_B_Rc(DCFFIXQ)
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TRANS_DFP_T_B_Rc(DCTFIX)
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TRANS_DFP_T_B_Rc(DCTFIXQ)
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TRANS_DFP_T_FPR_I32_Rc(DDEDPD, rb, sp)
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TRANS_DFP_T_FPR_I32_Rc(DDEDPDQ, rb, sp)
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TRANS_DFP_T_FPR_I32_Rc(DENBCD, rb, s)
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TRANS_DFP_T_FPR_I32_Rc(DENBCDQ, rb, s)
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TRANS_DFP_T_B_Rc(DXEX)
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TRANS_DFP_T_B_Rc(DXEXQ)
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TRANS_DFP_T_A_B_Rc(DIEX)
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TRANS_DFP_T_A_B_Rc(DIEXQ)
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TRANS_DFP_T_FPR_I32_Rc(DSCLI, ra, sh)
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TRANS_DFP_T_FPR_I32_Rc(DSCLIQ, ra, sh)
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TRANS_DFP_T_FPR_I32_Rc(DSCRI, ra, sh)
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TRANS_DFP_T_FPR_I32_Rc(DSCRIQ, ra, sh)
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static bool trans_DCFFIXQQ(DisasContext *ctx, arg_DCFFIXQQ *a)
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{
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TCGv_ptr rt, rb;
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REQUIRE_INSNS_FLAGS2(ctx, DFP);
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REQUIRE_FPU(ctx);
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REQUIRE_VECTOR(ctx);
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rt = gen_fprp_ptr(a->frtp);
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rb = gen_avr_ptr(a->vrb);
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gen_helper_DCFFIXQQ(cpu_env, rt, rb);
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tcg_temp_free_ptr(rt);
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tcg_temp_free_ptr(rb);
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return true;
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}
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static bool trans_DCTFIXQQ(DisasContext *ctx, arg_DCTFIXQQ *a)
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{
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TCGv_ptr rt, rb;
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REQUIRE_INSNS_FLAGS2(ctx, DFP);
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REQUIRE_FPU(ctx);
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REQUIRE_VECTOR(ctx);
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rt = gen_avr_ptr(a->vrt);
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rb = gen_fprp_ptr(a->frbp);
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gen_helper_DCTFIXQQ(cpu_env, rt, rb);
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tcg_temp_free_ptr(rt);
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tcg_temp_free_ptr(rb);
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return true;
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}
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