LIU Zhiwei 3e09396e36 target/riscv: fix vector index load/store constraints ... Although not explicitly specified that the the destination vector register groups cannot overlap the source vector register group, it is still necessary. And this constraint has been added to the v0.8 spec. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200721133742.2298-2-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2020-07-22 09:39:46 -07:00
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trans_privileged.inc.c	target/riscv: Move the hfence instructions to the rvh decode	2020-06-19 08:24:07 -07:00
trans_rva.inc.c	tcg: TCGMemOp is now accelerator independent MemOp	2019-09-03 08:30:38 -07:00
trans_rvd.inc.c	target/riscv: fsd/fsw doesn't dirty FP state	2020-01-16 10:03:08 -08:00
trans_rvf.inc.c	riscv: Add helper to make NaN-boxing for FP register	2020-06-19 08:24:07 -07:00
trans_rvh.inc.c	target/riscv: Implement checks for hfence	2020-06-19 08:24:07 -07:00
trans_rvi.inc.c	tcg: TCGMemOp is now accelerator independent MemOp	2019-09-03 08:30:38 -07:00
trans_rvm.inc.c	target/riscv: Zero extend the inputs of divuw and remuw	2019-03-22 00:26:39 -07:00
trans_rvv.inc.c	target/riscv: fix vector index load/store constraints	2020-07-22 09:39:46 -07:00