Add the parameter 'order' to qemu_register_reset and sort callbacks on registration. On system reset, callbacks with lower order will be invoked before those with higher order. Update all existing users to the standard order 0. Note: At least for x86, the existing users seem to assume that handlers are called in their registration order. Therefore, the patch preserves this property. If someone feels bored, (s)he could try to identify this dependency and express it properly on callback registration. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
222 lines
5.7 KiB
C
222 lines
5.7 KiB
C
/*
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* QEMU Sparc Sun4c interrupt controller emulation
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*
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* Based on slavio_intctl, copyright (c) 2003-2005 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "sun4m.h"
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#include "monitor.h"
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//#define DEBUG_IRQ_COUNT
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//#define DEBUG_IRQ
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#ifdef DEBUG_IRQ
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#define DPRINTF(fmt, ...) \
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do { printf("IRQ: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define DPRINTF(fmt, ...)
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#endif
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/*
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* Registers of interrupt controller in sun4c.
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*
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*/
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#define MAX_PILS 16
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typedef struct Sun4c_INTCTLState {
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#ifdef DEBUG_IRQ_COUNT
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uint64_t irq_count;
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#endif
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qemu_irq *cpu_irqs;
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const uint32_t *intbit_to_level;
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uint32_t pil_out;
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uint8_t reg;
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uint8_t pending;
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} Sun4c_INTCTLState;
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#define INTCTL_SIZE 1
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static void sun4c_check_interrupts(void *opaque);
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static uint32_t sun4c_intctl_mem_readb(void *opaque, target_phys_addr_t addr)
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{
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Sun4c_INTCTLState *s = opaque;
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uint32_t ret;
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ret = s->reg;
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DPRINTF("read reg 0x" TARGET_FMT_plx " = %x\n", addr, ret);
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return ret;
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}
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static void sun4c_intctl_mem_writeb(void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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Sun4c_INTCTLState *s = opaque;
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DPRINTF("write reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
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val &= 0xbf;
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s->reg = val;
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sun4c_check_interrupts(s);
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}
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static CPUReadMemoryFunc *sun4c_intctl_mem_read[3] = {
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sun4c_intctl_mem_readb,
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NULL,
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NULL,
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};
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static CPUWriteMemoryFunc *sun4c_intctl_mem_write[3] = {
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sun4c_intctl_mem_writeb,
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NULL,
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NULL,
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};
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void sun4c_pic_info(Monitor *mon, void *opaque)
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{
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Sun4c_INTCTLState *s = opaque;
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monitor_printf(mon, "master: pending 0x%2.2x, enabled 0x%2.2x\n",
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s->pending, s->reg);
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}
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void sun4c_irq_info(Monitor *mon, void *opaque)
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{
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#ifndef DEBUG_IRQ_COUNT
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monitor_printf(mon, "irq statistic code not compiled.\n");
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#else
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Sun4c_INTCTLState *s = opaque;
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int64_t count;
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monitor_printf(mon, "IRQ statistics:\n");
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count = s->irq_count[i];
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if (count > 0)
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monitor_printf(mon, "%2d: %" PRId64 "\n", i, count);
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#endif
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}
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static const uint32_t intbit_to_level[] = { 0, 1, 4, 6, 8, 10, 0, 14, };
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static void sun4c_check_interrupts(void *opaque)
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{
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Sun4c_INTCTLState *s = opaque;
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uint32_t pil_pending;
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unsigned int i;
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DPRINTF("pending %x disabled %x\n", pending, s->intregm_disabled);
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pil_pending = 0;
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if (s->pending && !(s->reg & 0x80000000)) {
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for (i = 0; i < 8; i++) {
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if (s->pending & (1 << i))
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pil_pending |= 1 << intbit_to_level[i];
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}
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}
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for (i = 0; i < MAX_PILS; i++) {
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if (pil_pending & (1 << i)) {
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if (!(s->pil_out & (1 << i)))
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qemu_irq_raise(s->cpu_irqs[i]);
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} else {
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if (s->pil_out & (1 << i))
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qemu_irq_lower(s->cpu_irqs[i]);
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}
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}
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s->pil_out = pil_pending;
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}
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/*
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* "irq" here is the bit number in the system interrupt register
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*/
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static void sun4c_set_irq(void *opaque, int irq, int level)
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{
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Sun4c_INTCTLState *s = opaque;
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uint32_t mask = 1 << irq;
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uint32_t pil = intbit_to_level[irq];
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DPRINTF("Set irq %d -> pil %d level %d\n", irq, pil,
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level);
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if (pil > 0) {
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if (level) {
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#ifdef DEBUG_IRQ_COUNT
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s->irq_count[pil]++;
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#endif
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s->pending |= mask;
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} else {
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s->pending &= ~mask;
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}
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sun4c_check_interrupts(s);
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}
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}
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static void sun4c_intctl_save(QEMUFile *f, void *opaque)
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{
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Sun4c_INTCTLState *s = opaque;
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qemu_put_8s(f, &s->reg);
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qemu_put_8s(f, &s->pending);
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}
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static int sun4c_intctl_load(QEMUFile *f, void *opaque, int version_id)
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{
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Sun4c_INTCTLState *s = opaque;
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if (version_id != 1)
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return -EINVAL;
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qemu_get_8s(f, &s->reg);
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qemu_get_8s(f, &s->pending);
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sun4c_check_interrupts(s);
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return 0;
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}
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static void sun4c_intctl_reset(void *opaque)
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{
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Sun4c_INTCTLState *s = opaque;
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s->reg = 1;
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s->pending = 0;
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sun4c_check_interrupts(s);
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}
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void *sun4c_intctl_init(target_phys_addr_t addr, qemu_irq **irq,
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qemu_irq *parent_irq)
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{
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int sun4c_intctl_io_memory;
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Sun4c_INTCTLState *s;
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s = qemu_mallocz(sizeof(Sun4c_INTCTLState));
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sun4c_intctl_io_memory = cpu_register_io_memory(0, sun4c_intctl_mem_read,
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sun4c_intctl_mem_write, s);
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cpu_register_physical_memory(addr, INTCTL_SIZE, sun4c_intctl_io_memory);
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s->cpu_irqs = parent_irq;
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register_savevm("sun4c_intctl", addr, 1, sun4c_intctl_save,
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sun4c_intctl_load, s);
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qemu_register_reset(sun4c_intctl_reset, 0, s);
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*irq = qemu_allocate_irqs(sun4c_set_irq, s, 8);
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sun4c_intctl_reset(s);
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return s;
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}
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